hdl.ast: deprecate Signal.{range,enum}.

Although constructor methods can improve clarity, there are many
contexts in which it is useful to use range() as a shape: notably
Layout, but also Const and AnyConst/AnyValue. Instead of duplicating
these constructor methods everywhere (which is not even easily
possible for Layout), use casting to Shape, introduced in 6aabdc0a.

Fixes #225.

nmigen/lib/coding.py

@@ -25,7 +25,7 @@ class Encoder(Elaboratable):
     ----------
     i : Signal(width), in
         One-hot input.
-    o : Signal.range(width), out
+    o : Signal(range(width)), out
         Encoded binary.
     n : Signal, out
         Invalid: either none or multiple input bits are asserted.
@@ -34,7 +34,7 @@ class Encoder(Elaboratable):
         self.width = width
 
         self.i = Signal(width)
-        self.o = Signal.range(width)
+        self.o = Signal(range(width))
         self.n = Signal()
 
     def elaborate(self, platform):
@@ -64,7 +64,7 @@ class PriorityEncoder(Elaboratable):
     ----------
     i : Signal(width), in
         Input requests.
-    o : Signal.range(width), out
+    o : Signal(range(width)), out
         Encoded binary.
     n : Signal, out
         Invalid: no input bits are asserted.
@@ -73,7 +73,7 @@ class PriorityEncoder(Elaboratable):
         self.width = width
 
         self.i = Signal(width)
-        self.o = Signal.range(width)
+        self.o = Signal(range(width))
         self.n = Signal()
 
     def elaborate(self, platform):
@@ -98,7 +98,7 @@ class Decoder(Elaboratable):
 
     Attributes
     ----------
-    i : Signal.range(width), in
+    i : Signal(range(width)), in
         Input binary.
     o : Signal(width), out
         Decoded one-hot.
@@ -108,7 +108,7 @@ class Decoder(Elaboratable):
     def __init__(self, width):
         self.width = width
 
-        self.i = Signal.range(width)
+        self.i = Signal(range(width))
         self.n = Signal()
         self.o = Signal(width)
 

nmigen/lib/fifo.py

@@ -187,7 +187,7 @@ class SyncFIFO(Elaboratable, FIFOInterface):
     def __init__(self, *, width, depth, fwft=True):
         super().__init__(width=width, depth=depth, fwft=fwft)
 
-        self.level = Signal.range(depth + 1)
+        self.level = Signal(range(depth + 1))
 
     def elaborate(self, platform):
         m = Module()
@@ -210,8 +210,8 @@ class SyncFIFO(Elaboratable, FIFOInterface):
         w_port  = m.submodules.w_port = storage.write_port()
         r_port  = m.submodules.r_port = storage.read_port(
             domain="comb" if self.fwft else "sync", transparent=self.fwft)
-        produce = Signal.range(self.depth)
-        consume = Signal.range(self.depth)
+        produce = Signal(range(self.depth))
+        consume = Signal(range(self.depth))
 
         m.d.comb += [
             w_port.addr.eq(produce),
@@ -289,7 +289,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface):
     def __init__(self, *, width, depth):
         super().__init__(width=width, depth=depth, fwft=True)
 
-        self.level = Signal.range(depth + 1)
+        self.level = Signal(range(depth + 1))
 
     def elaborate(self, platform):
         m = Module()