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fhdl.cd: rename ClockDomain signals together with domain.

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This commit is contained in:
whitequark 2018-12-13 15:24:55 +00:00
parent 07c818e077
commit 71f1f717c4
3 changed files with 33 additions and 3 deletions
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16
nmigen/test/test_fhdl_cd.py
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@ -4,8 +4,14 @@ from .tools import *
class ClockDomainCase(FHDLTestCase):
def test_name(self):
sync = ClockDomain()
self.assertEqual(sync.name, "sync")
self.assertEqual(sync.clk.name, "clk")
self.assertEqual(sync.rst.name, "rst")
pix = ClockDomain()
self.assertEqual(pix.name, "pix")
self.assertEqual(pix.clk.name, "pix_clk")
self.assertEqual(pix.rst.name, "pix_rst")
cd_pix = ClockDomain()
self.assertEqual(pix.name, "pix")
dom = [ClockDomain("foo")][0]
@ -31,3 +37,13 @@ class ClockDomainCase(FHDLTestCase):
self.assertIsNotNone(pix.clk)
self.assertIsNotNone(pix.rst)
self.assertTrue(pix.async_reset)
def test_rename(self):
sync = ClockDomain()
self.assertEqual(sync.name, "sync")
self.assertEqual(sync.clk.name, "clk")
self.assertEqual(sync.rst.name, "rst")
sync.rename("pix")
self.assertEqual(sync.name, "pix")
self.assertEqual(sync.clk.name, "pix_clk")
self.assertEqual(sync.rst.name, "pix_rst")