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hdl.dsl: add signal decoder to FSM state signal.

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whitequark 2018-12-26 09:45:12 +00:00
parent 54e3195dcb
commit 72039b6072
1 changed files with 2 additions and 0 deletions
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2
nmigen/hdl/dsl.py
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@ -298,6 +298,8 @@ class Module(_ModuleBuilderRoot):
fsm_signal, fsm_encoding, fsm_states = data["signal"], data["encoding"], data["states"]
fsm_signal.nbits = bits_for(len(fsm_encoding) - 1)
# The FSM is encoded such that the state with encoding 0 is always the reset state.
fsm_decoding = {n: s for s, n in fsm_encoding.items()}
fsm_signal.decoder = lambda v: "{}/{}".format(fsm_decoding[n], n)
self._statements.append(Switch(fsm_signal,
OrderedDict((fsm_encoding[name], stmts) for name, stmts in fsm_states.items())))