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fhdl.ir: implement clock domain propagation.

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This commit is contained in:
whitequark 2018-12-13 11:01:03 +00:00
parent fde2471963
commit 72257b6935
12 changed files with 324 additions and 46 deletions
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6
examples/arst.py
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@ -14,8 +14,8 @@ class ClockDivisor:
return m.lower(platform)
sync = ClockDomain(async_reset=True)
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sync.clk, sync.reset, ctr.o], clock_domains={"sync": sync}))
print(verilog.convert(frag, ports=[sync.clk, sync.reset, ctr.o], clock_domains={"sync": sync}))
frag.add_domains(ClockDomain("sync", async_reset=True))
# print(rtlil.convert(frag, ports=[ctr.o]))
print(verilog.convert(frag, ports=[ctr.o]))

5
examples/cdc.py
View file

@ -3,8 +3,7 @@ from nmigen.back import rtlil, verilog
from nmigen.genlib.cdc import *
sys = ClockDomain()
i, o = Signal(name="i"), Signal(name="o")
frag = MultiReg(i, o).get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[i, o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[i, o], clock_domains={"sys": sys}))
# print(rtlil.convert(frag, ports=[i, o]))
print(verilog.convert(frag, ports=[i, o]))

5
examples/clkdiv.py
View file

@ -14,8 +14,7 @@ class ClockDivisor:
return m.lower(platform)
sync = ClockDomain()
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sync.clk, ctr.o], clock_domains={"sync": sync}))
print(verilog.convert(frag, ports=[sync.clk, ctr.o], clock_domains={"sync": sync}))
# print(rtlil.convert(frag, ports=[ctr.o]))
print(verilog.convert(frag, ports=[ctr.o]))

5
examples/ctrl.py
View file

@ -15,8 +15,7 @@ class ClockDivisor:
return CEInserter(self.ce)(m.lower(platform))
sync = ClockDomain()
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))
print(verilog.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))
# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))