fhdl.ir: implement clock domain propagation.
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fde2471963
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12 changed files with 324 additions and 46 deletions
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@ -5,13 +5,13 @@ __all__ = ["MultiReg"]
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class MultiReg:
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def __init__(self, i, o, odomain="sys", n=2, reset=0):
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def __init__(self, i, o, odomain="sync", n=2, reset=0):
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self.i = i
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self.o = o
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self.odomain = odomain
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self._regs = [Signal(self.i.shape(), name="cdc{}".format(i), reset=reset, reset_less=True,
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attrs={"no_retiming": True})
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self._regs = [Signal(self.i.shape(), name="cdc{}".format(i),
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reset=reset, reset_less=True, attrs={"no_retiming": True})
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for i in range(n)]
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def get_fragment(self, platform):
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