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vendor.intel: double-quote Tcl values rather than brace-quoting.

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For unknown reasons, Quartus treats {foo} and "foo" in completely
different ways, which is not true for normal Tcl code; specifically,
it preserves the braces if they are used. Because of this, since
commit 6cee2804, the vendor.intel package was completely broken.
This commit is contained in:
whitequark 2020-05-21 09:48:42 +00:00
parent 702e41ba3c
commit 7238e58224
2 changed files with 11 additions and 7 deletions
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4
nmigen/build/plat.py
View file

@ -388,6 +388,9 @@ class TemplatedPlatform(Platform):
def tcl_escape(string):
return "{" + re.sub(r"([{}\\])", r"\\\1", string) + "}"
def tcl_quote(string):
return '"' + re.sub(r"([$[\\])", r"\\\1", string) + '"'
def verbose(arg):
if "NMIGEN_verbose" in os.environ:
return arg
@ -409,6 +412,7 @@ class TemplatedPlatform(Platform):
compiled.environment.filters["hierarchy"] = hierarchy
compiled.environment.filters["ascii_escape"] = ascii_escape
compiled.environment.filters["tcl_escape"] = tcl_escape
compiled.environment.filters["tcl_quote"] = tcl_quote
except jinja2.TemplateSyntaxError as e:
e.args = ("{} (at {}:{})".format(e.message, origin, e.lineno),)
raise

14
nmigen/vendor/intel.py vendored
View file

@ -85,22 +85,22 @@ class IntelPlatform(TemplatedPlatform):
{% endif %}
{% for file in platform.iter_extra_files(".v") -%}
set_global_assignment -name VERILOG_FILE {{file|tcl_escape}}
set_global_assignment -name VERILOG_FILE {{file|tcl_quote}}
{% endfor %}
{% for file in platform.iter_extra_files(".sv") -%}
set_global_assignment -name SYSTEMVERILOG_FILE {{file|tcl_escape}}
set_global_assignment -name SYSTEMVERILOG_FILE {{file|tcl_quote}}
{% endfor %}
{% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
set_global_assignment -name VHDL_FILE {{file|tcl_escape}}
set_global_assignment -name VHDL_FILE {{file|tcl_quote}}
{% endfor %}
set_global_assignment -name VERILOG_FILE {{name}}.v
set_global_assignment -name TOP_LEVEL_ENTITY {{name}}
set_global_assignment -name DEVICE {{platform.device}}{{platform.package}}{{platform.speed}}{{platform.suffix}}
{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
set_location_assignment -to {{port_name|tcl_escape}} PIN_{{pin_name}}
set_location_assignment -to {{port_name|tcl_quote}} PIN_{{pin_name}}
{% for key, value in attrs.items() -%}
set_instance_assignment -to {{port_name|tcl_escape}} -name {{key}} {{value|tcl_escape}}
set_instance_assignment -to {{port_name|tcl_quote}} -name {{key}} {{value|tcl_quote}}
{% endfor %}
{% endfor %}
@ -109,9 +109,9 @@ class IntelPlatform(TemplatedPlatform):
"{{name}}.sdc": r"""
{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
{% if port_signal is not none -%}
create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
create_clock -name {{port_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_quote}}]
{% else -%}
create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("|")|tcl_escape}}]
create_clock -name {{net_signal.name|tcl_quote}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("|")|tcl_quote}}]
{% endif %}
{% endfor %}
""",