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vendor.intel: silence meaningless warnings in nMigen files

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Dan Ravensloft 2019-12-01 00:07:48 +00:00 committed by whitequark
parent 7df70059d1
commit 72cfdb0c93
1 changed files with 16 additions and 0 deletions
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16
nmigen/vendor/intel.py vendored
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@ -38,6 +38,17 @@ class IntelPlatform(TemplatedPlatform):
speed = abstractproperty() speed = abstractproperty()
suffix = "" suffix = ""
quartus_suppressed_warnings = [
10264, # All case item expressions in this case statement are onehot
10270, # Incomplete Verilog case statement has no default case item
10335, # Unrecognized synthesis attribute
10763, # Verilog case statement has overlapping case item expressions with non-constant or don't care bits
10935, # Verilog casex/casez overlaps with a previous casex/vasez item expression
12125, # Using design file which is not specified as a design file for the current project, but contains definitions used in project
18236, # Number of processors not specified in QSF
292013, # Feature is only available with a valid subscription license
]
required_tools = [ required_tools = [
"quartus_map", "quartus_map",
"quartus_fit", "quartus_fit",
@ -100,6 +111,11 @@ class IntelPlatform(TemplatedPlatform):
create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("|")}}] create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("|")}}]
{% endfor %} {% endfor %}
""", """,
"{{name}}.srf": r"""
{% for warning in platform.quartus_suppressed_warnings %}
{ "" "" "" "{{name}}.v" { } { } 0 {{warning}} "" 0 0 "Design Software" 0 -1 0 ""}
{% endfor %}
""",
} }
command_templates = [ command_templates = [
r""" r"""