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27cedf4302
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7342662bee
2 changed files with 19 additions and 0 deletions
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@ -510,6 +510,17 @@ class SignalTestCase(FHDLTestCase):
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self.assertEqual(s1.reset, 0b111)
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self.assertEqual(s1.reset_less, True)
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def test_reset_narrow(self):
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with self.assertWarns(SyntaxWarning,
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msg="Reset value 8 requires 4 bits to represent, but the signal only has 3 bits"):
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Signal(3, reset=8)
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with self.assertWarns(SyntaxWarning,
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msg="Reset value 4 requires 4 bits to represent, but the signal only has 3 bits"):
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Signal((3, True), reset=4)
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with self.assertWarns(SyntaxWarning,
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msg="Reset value -5 requires 4 bits to represent, but the signal only has 3 bits"):
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Signal((3, True), reset=-5)
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def test_attrs(self):
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s1 = Signal()
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self.assertEqual(s1.attrs, {})
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