hdl.ast: warn if reset value is truncated.

Fixes #183.
This commit is contained in:
whitequark 2019-09-10 07:25:28 +00:00
parent 27cedf4302
commit 7342662bee
2 changed files with 19 additions and 0 deletions

View file

@ -510,6 +510,17 @@ class SignalTestCase(FHDLTestCase):
self.assertEqual(s1.reset, 0b111)
self.assertEqual(s1.reset_less, True)
def test_reset_narrow(self):
with self.assertWarns(SyntaxWarning,
msg="Reset value 8 requires 4 bits to represent, but the signal only has 3 bits"):
Signal(3, reset=8)
with self.assertWarns(SyntaxWarning,
msg="Reset value 4 requires 4 bits to represent, but the signal only has 3 bits"):
Signal((3, True), reset=4)
with self.assertWarns(SyntaxWarning,
msg="Reset value -5 requires 4 bits to represent, but the signal only has 3 bits"):
Signal((3, True), reset=-5)
def test_attrs(self):
s1 = Signal()
self.assertEqual(s1.attrs, {})