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hdl.ast: warn if reset value is truncated.

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Fixes #183.
This commit is contained in:
whitequark 2019-09-10 07:25:28 +00:00
parent 27cedf4302
commit 7342662bee
2 changed files with 19 additions and 0 deletions
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8
nmigen/hdl/ast.py
View file

@ -665,6 +665,14 @@ class Signal(Value, DUID):
if not isinstance(self.nbits, int) or self.nbits < 0: if not isinstance(self.nbits, int) or self.nbits < 0:
raise TypeError("Width must be a non-negative integer, not '{!r}'".format(self.nbits)) raise TypeError("Width must be a non-negative integer, not '{!r}'".format(self.nbits))
reset_nbits = bits_for(reset, self.signed)
if reset != 0 and reset_nbits > self.nbits:
warnings.warn("Reset value {!r} requires {} bits to represent, but the signal "
"only has {} bits"
.format(reset, reset_nbits, self.nbits),
SyntaxWarning, stacklevel=2 + src_loc_at)
self.reset = int(reset) self.reset = int(reset)
self.reset_less = bool(reset_less) self.reset_less = bool(reset_less)

11
nmigen/test/test_hdl_ast.py
View file

@ -510,6 +510,17 @@ class SignalTestCase(FHDLTestCase):
self.assertEqual(s1.reset, 0b111) self.assertEqual(s1.reset, 0b111)
self.assertEqual(s1.reset_less, True) self.assertEqual(s1.reset_less, True)
def test_reset_narrow(self):
with self.assertWarns(SyntaxWarning,
msg="Reset value 8 requires 4 bits to represent, but the signal only has 3 bits"):
Signal(3, reset=8)
with self.assertWarns(SyntaxWarning,
msg="Reset value 4 requires 4 bits to represent, but the signal only has 3 bits"):
Signal((3, True), reset=4)
with self.assertWarns(SyntaxWarning,
msg="Reset value -5 requires 4 bits to represent, but the signal only has 3 bits"):
Signal((3, True), reset=-5)
def test_attrs(self): def test_attrs(self):
s1 = Signal() s1 = Signal()
self.assertEqual(s1.attrs, {}) self.assertEqual(s1.attrs, {})