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hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements

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Thomas Watson 2021-05-10 20:59:34 -05:00 • committed by whitequark
parent d824795c2c
commit 7443f89200
2 changed files with 31 additions and 2 deletions
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28
tests/test_hdl_dsl.py
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@ -281,6 +281,34 @@ class DSLTestCase(FHDLTestCase):
with m.Else():
pass
def test_Else_wrong_nested(self):
m = Module()
with m.If(self.s1):
with self.assertRaisesRegex(SyntaxError,
r"^Else without preceding If/Elif$"):
with m.Else():
pass
def test_Elif_Elif_wrong_nested(self):
m = Module()
with m.If(self.s1):
pass
with m.Elif(self.s2):
with self.assertRaisesRegex(SyntaxError,
r"^Elif without preceding If$"):
with m.Elif(self.s3):
pass
def test_Else_Else_wrong_nested(self):
m = Module()
with m.If(self.s1):
pass
with m.Else():
with self.assertRaisesRegex(SyntaxError,
r"^Else without preceding If/Elif$"):
with m.Else():
pass
def test_If_wide(self):
m = Module()
with m.If(self.w1):