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hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements

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This commit is contained in:
Thomas Watson 2021-05-10 20:59:34 -05:00 committed by whitequark
parent d824795c2c
commit 7443f89200
2 changed files with 31 additions and 2 deletions
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5
nmigen/hdl/dsl.py
View file

@ -226,6 +226,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
cond = self._check_signed_cond(cond)
src_loc = tracer.get_src_loc(src_loc_at=1)
if_data = self._set_ctrl("If", {
"depth": self.domain._depth,
"tests": [],
"bodies": [],
"src_loc": src_loc,
@ -249,7 +250,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
cond = self._check_signed_cond(cond)
src_loc = tracer.get_src_loc(src_loc_at=1)
if_data = self._get_ctrl("If")
if if_data is None or len(if_data["tests"]) == 0:
if if_data is None or if_data["depth"] != self.domain._depth:
raise SyntaxError("Elif without preceding If")
try:
_outer_case, self._statements = self._statements, []
@ -268,7 +269,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
self._check_context("Else", context=None)
src_loc = tracer.get_src_loc(src_loc_at=1)
if_data = self._get_ctrl("If")
if if_data is None:
if if_data is None or if_data["depth"] != self.domain._depth:
raise SyntaxError("Else without preceding If/Elif")
try:
_outer_case, self._statements = self._statements, []

28
tests/test_hdl_dsl.py
View file

@ -281,6 +281,34 @@ class DSLTestCase(FHDLTestCase):
with m.Else():
pass
def test_Else_wrong_nested(self):
m = Module()
with m.If(self.s1):
with self.assertRaisesRegex(SyntaxError,
r"^Else without preceding If/Elif$"):
with m.Else():
pass
def test_Elif_Elif_wrong_nested(self):
m = Module()
with m.If(self.s1):
pass
with m.Elif(self.s2):
with self.assertRaisesRegex(SyntaxError,
r"^Elif without preceding If$"):
with m.Elif(self.s3):
pass
def test_Else_Else_wrong_nested(self):
m = Module()
with m.If(self.s1):
pass
with m.Else():
with self.assertRaisesRegex(SyntaxError,
r"^Else without preceding If/Elif$"):
with m.Else():
pass
def test_If_wide(self):
m = Module()
with m.If(self.w1):