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hdl._mem: implement MemoryData._Row from RFC 62.

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Wanda 2024-04-03 17:12:56 +02:00 • committed by Catherine
parent 93ef89626e
commit 767d69c703
11 changed files with 214 additions and 83 deletions
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28
tests/test_hdl_mem.py
View file

@ -1,12 +1,38 @@
# amaranth: UnusedElaboratable=no
from amaranth.hdl._ast import *
from amaranth.hdl import *
from amaranth.hdl._mem import *
from amaranth._utils import _ignore_deprecated
from .utils import *
class MemoryDataTestCase(FHDLTestCase):
def test_repr(self):
data = MemoryData(shape=8, depth=4, init=[])
self.assertRepr(data, "(memory-data data)")
def test_row(self):
data = MemoryData(shape=8, depth=4, init=[])
self.assertRepr(data[2], "(memory-row (memory-data data) 2)")
def test_row_wrong(self):
data = MemoryData(shape=8, depth=4, init=[])
with self.assertRaisesRegex(IndexError,
r"^Index 4 is out of bounds \(memory has 4 rows\)$"):
data[4]
def test_row_elab(self):
data = MemoryData(shape=8, depth=4, init=[])
m = Module()
a = Signal(8)
with self.assertRaisesRegex(ValueError,
r"^Value \(memory-row \(memory-data data\) 0\) can only be used in simulator processes$"):
m.d.comb += a.eq(data[0])
with self.assertRaisesRegex(ValueError,
r"^Value \(memory-row \(memory-data data\) 0\) can only be used in simulator processes$"):
m.d.comb += data[0].eq(1)
class MemoryTestCase(FHDLTestCase):
def test_name(self):
with _ignore_deprecated():

28
tests/test_sim.py
View file

@ -1043,17 +1043,19 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
self.setUp_memory()
with self.assertSimulation(self.m) as sim:
def process():
self.assertEqual((yield self.memory[1]), 0x55)
self.assertEqual((yield self.memory[Const(1)]), 0x55)
self.assertEqual((yield self.memory[Const(2)]), 0x00)
yield self.memory[Const(1)].eq(Const(0x33))
self.assertEqual((yield self.memory[Const(1)]), 0x33)
self.assertEqual((yield self.memory.data[1]), 0x55)
self.assertEqual((yield self.memory.data[1]), 0x55)
self.assertEqual((yield self.memory.data[2]), 0x00)
yield self.memory.data[1].eq(Const(0x33))
self.assertEqual((yield self.memory.data[1]), 0x33)
yield self.memory.data[1][2:5].eq(Const(0x7))
self.assertEqual((yield self.memory.data[1]), 0x3f)
yield self.wrport.addr.eq(3)
yield self.wrport.data.eq(0x22)
yield self.wrport.en.eq(1)
self.assertEqual((yield self.memory[Const(3)]), 0)
self.assertEqual((yield self.memory.data[3]), 0)
yield Tick()
self.assertEqual((yield self.memory[Const(3)]), 0x22)
self.assertEqual((yield self.memory.data[3]), 0x22)
sim.add_clock(1e-6)
sim.add_testbench(process)
@ -1062,13 +1064,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
self.setUp_memory()
with self.assertSimulation(self.m) as sim:
def process():
self.assertEqual((yield self.memory[1]), 0x55)
self.assertEqual((yield self.memory[Const(1)]), 0x55)
self.assertEqual((yield self.memory[Const(2)]), 0x00)
yield self.memory[Const(1)].eq(Const(0x33))
self.assertEqual((yield self.memory[Const(1)]), 0x55)
self.assertEqual((yield self.memory.data[1]), 0x55)
self.assertEqual((yield self.memory.data[1]), 0x55)
self.assertEqual((yield self.memory.data[2]), 0x00)
yield self.memory.data[1].eq(Const(0x33))
self.assertEqual((yield self.memory.data[1]), 0x55)
yield Tick()
self.assertEqual((yield self.memory[Const(1)]), 0x33)
self.assertEqual((yield self.memory.data[1]), 0x33)
sim.add_clock(1e-6)
sim.add_process(process)