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hdl._dsl: raise an error when modifying an already-elaborated Module.

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This renames the `FrozenMemory` exception to `AlreadyElaborated`
and reuses it for modules.

Fixes #1350.
This commit is contained in:
Wanda 2024-05-08 01:15:35 +02:00 • committed by Catherine
parent 1d03c3498d
commit 77dab7884c
8 changed files with 73 additions and 28 deletions
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33
tests/test_hdl_dsl.py
View file

@ -6,6 +6,7 @@ from collections import OrderedDict
from amaranth.hdl._ast import *
from amaranth.hdl._cd import *
from amaranth.hdl._dsl import *
from amaranth.hdl._ir import *
from amaranth.lib.enum import Enum
from .utils import *
@ -975,3 +976,35 @@ class DSLTestCase(FHDLTestCase):
r"^Domain name should not be prefixed with 'cd_' in `m.domains`, "
r"use `m.domains.rx = ...` instead$"):
m.domains.cd_rx = ClockDomain()
def test_freeze(self):
a = Signal()
m = Module()
f = Fragment.get(m, None)
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot modify a module that has already been elaborated$"):
m.d.comb += a.eq(1)
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot modify a module that has already been elaborated$"):
with m.If(a):
pass
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot modify a module that has already been elaborated$"):
with m.Switch(a):
pass
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot modify a module that has already been elaborated$"):
with m.FSM():
pass
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot modify a module that has already been elaborated$"):
m.submodules.a = Module()
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot modify a module that has already been elaborated$"):
m.domains.sync = ClockDomain()

8
tests/test_lib_memory.py
View file

@ -439,15 +439,15 @@ class MemoryTestCase(FHDLTestCase):
m = memory.Memory(shape=unsigned(8), depth=4, init=[])
m.write_port()
m.elaborate(None)
with self.assertRaisesRegex(memory.FrozenMemory,
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot add a memory port to a memory that has already been elaborated$"):
m.write_port()
with self.assertRaisesRegex(memory.FrozenMemory,
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot add a memory port to a memory that has already been elaborated$"):
m.read_port()
with self.assertRaisesRegex(memory.FrozenMemory,
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot set 'init' on a memory that has already been elaborated$"):
m.init = [1, 2, 3, 4]
with self.assertRaisesRegex(memory.FrozenMemory,
with self.assertRaisesRegex(AlreadyElaborated,
r"^Cannot set 'init' on a memory that has already been elaborated$"):
m.init[0] = 1