sim: document.
This commit includes additional non-documentation changes, related to issues found while documenting it: - `Simulator.run_until()` no longer accepts a `run_passive=` argument. Passive no longer exist and in any case defaulting to `False` does not make a lot of sense from an API perspective. - `add_clock()`'s `phase=` argument, when specified, no longer has `period/2` added to it. This wasn't the documented behavior in first place and it makes no sense to do that. - `add_clock()` raises a `NameError` if a clock domain does not exist, instead of `ValueError`. - `add_clock()` raises a `DriverConflict` if a clock domain is already being driven by a clock, instead of `ValueError`. - GTKWave is no longer a part of the installation instructions, and both Surfer and GTKWave are recommended (in this order).
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@ -171,21 +171,35 @@ However, the memory read port is also configured to be *transparent* relative to
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Simulation
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==========
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++++++++++
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.. todo::
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There are two ways to interact with a memory array in a simulator: requesting a read and/or write port that is used only in a testbench, or directly reading and writing memory contents. In most cases, directly accessing memory contents using :meth:`MemoryData.__getitem__ <amaranth.hdl.MemoryData.__getitem__>` is more convenient.
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This section will be written once the simulator itself is documented.
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For example, this :doc:`testbench </simulator>` will clear the least significant bit of every memory row:
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.. testcode::
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async def testbench(ctx):
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for index in len(memory.data):
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ctx.set(memory.data[index], ctx.get(memory.data[index]) & ~1)
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Memory description
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==================
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.. autoexception:: amaranth.hdl.AlreadyElaborated
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:noindex:
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:noindex:
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..
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:canonical: amaranth.hdl.AlreadyElaborated
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(not available until `amaranth.hdl` documents it)
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.. autoclass:: amaranth.hdl.MemoryData
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..
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:canonical: amaranth.hdl.MemoryData
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(not available until `amaranth.hdl` documents it)
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Memory component
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================
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