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test.compat: reenable tests converting to Verilog.

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whitequark 2019-01-26 15:29:09 +00:00
parent 4887771e4a
commit 7890c0adc8
2 changed files with 4 additions and 4 deletions
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2
nmigen/compat/fhdl/verilog.py
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@ -1,6 +1,6 @@
import warnings
from ...hdl import Fragment
from ...hdl.ir import Fragment
from ...back import verilog
from .conv_output import ConvOutput