test.compat: reenable tests converting to Verilog.

nmigen/compat/fhdl/verilog.py

@@ -1,6 +1,6 @@
 import warnings
 
-from ...hdl import Fragment
+from ...hdl.ir import Fragment
 from ...back import verilog
 from .conv_output import ConvOutput
 

nmigen/test/compat/support.py

@@ -1,13 +1,13 @@
 from ...compat import *
-# from ...compat.fhdl import verilog
+from ...compat.fhdl import verilog
 
 
 class SimCase:
     def setUp(self, *args, **kwargs):
         self.tb = self.TestBench(*args, **kwargs)
 
-    # def test_to_verilog(self):
-    #     verilog.convert(self.tb)
+    def test_to_verilog(self):
+        verilog.convert(self.tb)
 
     def run_with(self, generator):
         run_simulation(self.tb, generator)