hdl.xfrm: add assignment legalizer.
Co-authored-by: Wanda <wanda@phinode.net>
This commit is contained in:
Catherine
parent
10117607a3
commit
78981232d9
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@ -17,7 +17,7 @@ __all__ = ["ValueVisitor", "ValueTransformer",
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"TransformedElaboratable",
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"DomainCollector", "DomainRenamer", "DomainLowerer",
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"SwitchCleaner", "LHSGroupAnalyzer", "LHSGroupFilter",
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"ResetInserter", "EnableInserter"]
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"ResetInserter", "EnableInserter", "AssignmentLegalizer"]
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class ValueVisitor(metaclass=ABCMeta):
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@ -670,3 +670,85 @@ class EnableInserter(_ControlInserter):
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if port._domain in self.controls:
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port._en = Mux(self.controls[port._domain], port._en, Const(0, len(port._en)))
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return new_fragment
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class AssignmentLegalizer(FragmentTransformer, StatementTransformer):
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"""Ensures all assignments in switches have one of the following on the LHS:
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- a `Signal`
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- a `Slice` with `value` that is a `Signal`
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"""
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def emit_assign(self, lhs, rhs, lhs_start=0, lhs_stop=None):
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if isinstance(lhs, ArrayProxy):
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# Lower into a switch.
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cases = {}
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for idx, val in enumerate(lhs.elems):
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cases[idx] = self.emit_assign(val, rhs, lhs_start, lhs_stop)
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return [Switch(lhs.index, cases)]
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elif isinstance(lhs, Part):
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offset = lhs.offset
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width = lhs.width
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if lhs_start != 0:
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width -= lhs_start
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if lhs_stop is not None:
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width = lhs_stop - lhs_start
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cases = {}
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lhs_width = len(lhs.value)
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for idx in range(lhs_width):
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start = lhs_start + idx * lhs.stride
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if start >= lhs_width:
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break
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stop = min(start + width, lhs_width)
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cases[idx] = self.emit_assign(lhs.value, rhs, start, stop)
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return [Switch(offset, cases)]
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elif isinstance(lhs, Slice):
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part_start = lhs_start + lhs.start
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if lhs_stop is not None:
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part_stop = lhs_stop + lhs.start
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else:
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part_stop = lhs_start + lhs.stop
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return self.emit_assign(lhs.value, rhs, part_start, part_stop)
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elif isinstance(lhs, Cat):
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# Split into several assignments.
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part_stop = 0
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res = []
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if lhs_stop is None:
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lhs_len = len(lhs) - lhs_start
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else:
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lhs_len = lhs_stop - lhs_start
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if len(rhs) < lhs_len:
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rhs |= Const(0, Shape(lhs_len, signed=rhs.shape().signed))
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for val in lhs.parts:
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part_start = part_stop
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part_len = len(val)
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part_stop = part_start + part_len
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if lhs_start >= part_stop:
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continue
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if lhs_start < part_start:
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part_lhs_start = 0
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part_rhs_start = part_start - lhs_start
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else:
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part_lhs_start = lhs_start - part_start
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part_rhs_start = 0
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if lhs_stop is not None and lhs_stop <= part_start:
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continue
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elif lhs_stop is None or lhs_stop >= part_stop:
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part_lhs_stop = None
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else:
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part_lhs_stop = lhs_stop - part_start
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res += self.emit_assign(val, rhs[part_rhs_start:], part_lhs_start, part_lhs_stop)
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return res
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elif isinstance(lhs, Signal):
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# Already ok.
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if lhs_start != 0 or lhs_stop is not None:
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return [Assign(lhs[lhs_start:lhs_stop], rhs)]
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else:
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return [Assign(lhs, rhs)]
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elif isinstance(lhs, Operator):
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assert lhs.operator in ('u', 's')
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return self.emit_assign(lhs.operands[0], rhs, lhs_start, lhs_stop)
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else:
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raise TypeError
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def on_Assign(self, stmt):
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return self.emit_assign(stmt.lhs, stmt.rhs)
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@ -547,6 +547,329 @@ class EnableInserterTestCase(FHDLTestCase):
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""")
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class AssignmentLegalizerTestCase(FHDLTestCase):
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def test_simple(self):
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s1 = Signal(8)
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s2 = Signal(8)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((eq (sig s1) (sig s2)))
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""")
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def test_simple_slice(self):
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s1 = Signal(8)
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s2 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1[2:6].eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((eq (slice (sig s1) 2:6) (sig s2)))
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""")
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def test_simple_part(self):
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s1 = Signal(8)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.bit_select(s3, 4).eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 0:4) (sig s2)))
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(case 0001 (eq (slice (sig s1) 1:5) (sig s2)))
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(case 0010 (eq (slice (sig s1) 2:6) (sig s2)))
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(case 0011 (eq (slice (sig s1) 3:7) (sig s2)))
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(case 0100 (eq (slice (sig s1) 4:8) (sig s2)))
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(case 0101 (eq (slice (sig s1) 5:8) (sig s2)))
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(case 0110 (eq (slice (sig s1) 6:8) (sig s2)))
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(case 0111 (eq (slice (sig s1) 7:8) (sig s2)))
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))
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""")
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def test_simple_part_word(self):
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s1 = Signal(8)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.word_select(s3, 4).eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 0:4) (sig s2)))
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(case 0001 (eq (slice (sig s1) 4:8) (sig s2)))
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))
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""")
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def test_simple_concat(self):
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s1 = Signal(4)
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s2 = Signal(4)
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s3 = Signal(4)
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s4 = Signal(12)
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f = Fragment()
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f.add_statements(
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"sync",
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Cat(s1, s2, s3).eq(s4)
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)
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f.add_driver(s3, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (slice (sig s4) 0:12))
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(eq (sig s2) (slice (sig s4) 4:12))
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(eq (sig s3) (slice (sig s4) 8:12))
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)
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""")
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def test_simple_concat_narrow(self):
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s1 = Signal(4)
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s2 = Signal(4)
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s3 = Signal(4)
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s4 = Signal(signed(6))
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f = Fragment()
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f.add_statements(
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"sync",
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Cat(s1, s2, s3).eq(s4)
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)
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f.add_driver(s3, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (slice (| (sig s4) (const 12'sd0)) 0:12))
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(eq (sig s2) (slice (| (sig s4) (const 12'sd0)) 4:12))
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(eq (sig s3) (slice (| (sig s4) (const 12'sd0)) 8:12))
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)
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""")
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def test_simple_operator(self):
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s1 = Signal(8)
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s2 = Signal(8)
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s3 = Signal(8)
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f = Fragment()
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f.add_statements("sync", [
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s1.as_signed().eq(s3),
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s2.as_unsigned().eq(s3),
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])
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (sig s1) (sig s3))
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(eq (sig s2) (sig s3))
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)
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""")
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def test_simple_array(self):
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s1 = Signal(8)
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s2 = Signal(8)
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s3 = Signal(8)
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s4 = Signal(8)
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s5 = Signal(8)
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f = Fragment()
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f.add_statements("sync", [
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Array([s1, s2, s3])[s4].eq(s5),
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])
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f.add_driver(s3, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s4)
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(case 00000000 (eq (sig s1) (sig s5)))
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(case 00000001 (eq (sig s2) (sig s5)))
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(case 00000010 (eq (sig s3) (sig s5)))
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))
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""")
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def test_sliced_slice(self):
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s1 = Signal(12)
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s2 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1[1:11][2:6].eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((eq (slice (sig s1) 3:7) (sig s2)))
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""")
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def test_sliced_concat(self):
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s1 = Signal(4)
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s2 = Signal(4)
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s3 = Signal(4)
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s4 = Signal(4)
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s5 = Signal(4)
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s6 = Signal(8)
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f = Fragment()
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f.add_statements(
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"sync",
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Cat(s1, s2, s3, s4, s5)[5:14].eq(s6)
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)
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f.add_driver(s3, "sync")
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f.add_driver(s4, "sync")
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f.add_driver(s5, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (slice (sig s2) 1:4) (slice (| (sig s6) (const 9'd0)) 0:9))
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(eq (sig s3) (slice (| (sig s6) (const 9'd0)) 3:9))
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(eq (slice (sig s4) 0:2) (slice (| (sig s6) (const 9'd0)) 7:9))
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)
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""")
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def test_sliced_part(self):
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s1 = Signal(8)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.bit_select(s3, 4)[1:3].eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 1:3) (sig s2)))
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(case 0001 (eq (slice (sig s1) 2:4) (sig s2)))
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(case 0010 (eq (slice (sig s1) 3:5) (sig s2)))
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(case 0011 (eq (slice (sig s1) 4:6) (sig s2)))
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(case 0100 (eq (slice (sig s1) 5:7) (sig s2)))
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(case 0101 (eq (slice (sig s1) 6:8) (sig s2)))
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(case 0110 (eq (slice (sig s1) 7:8) (sig s2)))
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))
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""")
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def test_sliced_part_word(self):
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s1 = Signal(8)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1.word_select(s3, 4)[1:3].eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 1:3) (sig s2)))
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(case 0001 (eq (slice (sig s1) 5:7) (sig s2)))
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))
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""")
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def test_sliced_array(self):
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s1 = Signal(8)
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s2 = Signal(8)
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s3 = Signal(8)
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s4 = Signal(8)
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s5 = Signal(8)
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f = Fragment()
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f.add_statements("sync", [
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Array([s1, s2, s3])[s4][2:7].eq(s5),
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])
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f.add_driver(s3, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s4)
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(case 00000000 (eq (slice (sig s1) 2:7) (sig s5)))
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(case 00000001 (eq (slice (sig s2) 2:7) (sig s5)))
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(case 00000010 (eq (slice (sig s3) 2:7) (sig s5)))
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))
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""")
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def test_part_slice(self):
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s1 = Signal(8)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1[1:7].bit_select(s3, 4).eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 1:5) (sig s2)))
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(case 0001 (eq (slice (sig s1) 2:6) (sig s2)))
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(case 0010 (eq (slice (sig s1) 3:7) (sig s2)))
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(case 0011 (eq (slice (sig s1) 4:7) (sig s2)))
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(case 0100 (eq (slice (sig s1) 5:7) (sig s2)))
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(case 0101 (eq (slice (sig s1) 6:7) (sig s2)))
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))
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""")
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def test_sliced_part_slice(self):
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s1 = Signal(12)
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s2 = Signal(4)
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s3 = Signal(4)
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f = Fragment()
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f.add_statements(
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"sync",
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s1[3:9].bit_select(s3, 4)[1:3].eq(s2)
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)
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f.add_driver(s1, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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((switch (sig s3)
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(case 0000 (eq (slice (sig s1) 4:6) (sig s2)))
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(case 0001 (eq (slice (sig s1) 5:7) (sig s2)))
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(case 0010 (eq (slice (sig s1) 6:8) (sig s2)))
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(case 0011 (eq (slice (sig s1) 7:9) (sig s2)))
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(case 0100 (eq (slice (sig s1) 8:9) (sig s2)))
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))
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""")
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def test_sliced_operator(self):
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s1 = Signal(8)
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s2 = Signal(8)
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s3 = Signal(8)
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f = Fragment()
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f.add_statements("sync", [
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s1.as_signed()[2:7].eq(s3),
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s2.as_unsigned()[2:7].eq(s3),
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])
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f.add_driver(s1, "sync")
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f.add_driver(s2, "sync")
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f = AssignmentLegalizer()(f)
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self.assertRepr(f.statements["sync"], """
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(
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(eq (slice (sig s1) 2:7) (sig s3))
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(eq (slice (sig s2) 2:7) (sig s3))
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)
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""")
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class _MockElaboratable(Elaboratable):
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def __init__(self):
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self.s1 = Signal()
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