Rename fhdl→hdl, genlib→lib.

doc/COMPAT_SUMMARY.md

@@ -27,13 +27,13 @@ Status legend:
 Compatibility summary
 ---------------------
 
-  - (−) `fhdl`
+  - (−) `fhdl` → `.hdl`
     - (+) `bitcontainer` ⇒ `.tools`
       - (+) `log2_int` id
       - (+) `bits_for` id
       - (+) `value_bits_sign` → `Value.shape`
     - (−) `conv_output` ?
-    - (+) `decorators` ⇒ `.fhdl.xfrm`
+    - (+) `decorators` ⇒ `.hdl.xfrm`
       <br>Note: `transform_*` methods not considered part of public API.
       - (⊙) `ModuleTransformer` **brk**
       - (⊙) `ControlInserter` **brk**
@@ -41,9 +41,9 @@ Compatibility summary
       - (+) `ResetInserter` id, `clock_domains=`→`controls=`
       - (+) `ClockDomainsRenamer` → `DomainRenamer`, `cd_remapping=`→`domain_map=`
     - (⊙) `edif` **brk**
-    - (+) `module` **obs** → `.fhdl.dsl`
+    - (+) `module` **obs** → `.hdl.dsl`
       - (+) `FinalizeError` **obs**
-      - (+) `Module` **obs** → `.fhdl.dsl.Module`
+      - (+) `Module` **obs** → `.hdl.dsl.Module`
     - (⊙) `namer` **brk**
     - (−) `simplify` ?
       - (−) `FullMemoryWE` ?
@@ -52,12 +52,12 @@ Compatibility summary
     - (−) `specials` **obs**
       - (−) `Special` ?
       - (−) `Tristate` ?
-      - (+) `TSTriple` → `.genlib.io.TSTriple`, `bits_sign=`→`shape=`
+      - (+) `TSTriple` → `.lib.io.TSTriple`, `bits_sign=`→`shape=`
       - (−) `Instance` ?
       - (−) `READ_FIRST`/`WRITE_FIRST`/`NO_CHANGE` ?
       - (−) `_MemoryPort` ?
       - (−) `Memory` ?
-    - (−) `structure` → `.fhdl.ast`
+    - (−) `structure` → `.hdl.ast`
       - (+) `DUID` id
       - (+) `_Value` → `Value`
         <br>Note: values no longer valid as keys in `dict` and `set`; use `ValueDict` and `ValueSet` instead.
@@ -75,14 +75,14 @@ Compatibility summary
       - (+) `_Statement` → `Statement`
       - (+) `_Assign` → `Assign`, `l=`→`lhs=`, `r=`→`rhs=`
       - (-) `_check_statement` **obs** → `Statement.wrap`
-      - (+) `If` **obs** → `.fhdl.dsl.Module.If`
-      - (+) `Case` **obs** → `.fhdl.dsl.Module.Switch`
+      - (+) `If` **obs** → `.hdl.dsl.Module.If`
+      - (+) `Case` **obs** → `.hdl.dsl.Module.Switch`
       - (−) `_ArrayProxy` ?
       - (−) `Array` ?
-      - (+) `ClockDomain` → `.fhdl.cd.ClockDomain`
+      - (+) `ClockDomain` → `.hdl.cd.ClockDomain`
       - (−) `_ClockDomainList` ?
       - (−) `SPECIAL_INPUT`/`SPECIAL_OUTPUT`/`SPECIAL_INOUT` ?
-      - (⊙) `_Fragment` **brk** → `.fhdl.ir.Fragment`
+      - (⊙) `_Fragment` **brk** → `.hdl.ir.Fragment`
     - (−) `tools` **brk**
       - (−) `list_signals` ?
       - (−) `list_targets` ?
@@ -94,12 +94,12 @@ Compatibility summary
       - (−) `is_variable` ?
       - (⊙) `generate_reset` **brk**
       - (⊙) `insert_reset` **brk**
-      - (⊙) `insert_resets` **brk** → `.fhdl.xfrm.ResetInserter`
+      - (⊙) `insert_resets` **brk** → `.hdl.xfrm.ResetInserter`
       - (⊙) `lower_basics` **brk**
       - (⊙) `lower_complex_slices` **brk**
       - (⊙) `lower_complex_parts` **brk**
       - (⊙) `rename_clock_domain_expr` **brk**
-      - (⊙) `rename_clock_domain` **brk** → `.fhdl.xfrm.DomainRenamer`
+      - (⊙) `rename_clock_domain` **brk** → `.hdl.xfrm.DomainRenamer`
       - (⊙) `call_special_classmethod` **brk**
       - (⊙) `lower_specials` **brk**
     - (−) `tracer` **brk**
@@ -111,10 +111,10 @@ Compatibility summary
     - (−) `verilog`
       - (−) `DummyAttrTranslate` ?
       - (−) `convert` **obs** → `.back.verilog.convert`
-    - (⊙) `visit` **brk** → `.fhdl.xfrm`
+    - (⊙) `visit` **brk** → `.hdl.xfrm`
       - (⊙) `NodeVisitor` **brk**
-      - (⊙) `NodeTransformer` **brk** → `.fhdl.xfrm.ValueTransformer`/`.fhdl.xfrm.StatementTransformer`
-  - (−) `genlib`
+      - (⊙) `NodeTransformer` **brk** → `.hdl.xfrm.ValueTransformer`/`.hdl.xfrm.StatementTransformer`
+  - (−) `genlib` → `.lib`
     - (−) `cdc` ?
       - (−) `MultiRegImpl` ?
       - (+) `MultiReg` id
@@ -177,7 +177,7 @@ Compatibility summary
     - (⊙) `vcd` **brk** → `vcd`
     - (⊙) `Simulator` **brk**
     - (+) `run_simulation` **obs** → `.back.pysim.Simulator`
-    - (−) `passive` **obs** → `.fhdl.ast.Passive`
+    - (−) `passive` **obs** → `.hdl.ast.Passive`
   - (−) `build` ?
   - (+) `util` **obs**
     - (+) `misc` ⇒ `.tools`

nmigen/__init__.py

@@ -1,7 +1,7 @@
-from .fhdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
-from .fhdl.dsl import Module
-from .fhdl.cd import ClockDomain
-from .fhdl.ir import Fragment
-from .fhdl.xfrm import ResetInserter, CEInserter
+from .hdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
+from .hdl.dsl import Module
+from .hdl.cd import ClockDomain
+from .hdl.ir import Fragment
+from .hdl.xfrm import ResetInserter, CEInserter
 
-from .genlib.cdc import MultiReg
+from .lib.cdc import MultiReg

nmigen/back/pysim.py

@@ -5,8 +5,8 @@ from vcd import VCDWriter
 from vcd.gtkw import GTKWSave
 
 from ..tools import flatten
-from ..fhdl.ast import *
-from ..fhdl.xfrm import ValueTransformer, StatementTransformer
+from ..hdl.ast import *
+from ..hdl.xfrm import ValueTransformer, StatementTransformer
 
 
 __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]

nmigen/back/rtlil.py

@@ -3,7 +3,7 @@ import textwrap
 from collections import defaultdict, OrderedDict
 from contextlib import contextmanager
 
-from ..fhdl import ast, ir, xfrm
+from ..hdl import ast, ir, xfrm
 
 
 class _Namer:

nmigen/compat/fhdl/bitcontainer.py

@@ -1,5 +1,5 @@
 from ... import tools
-from ...fhdl import ast
+from ...hdl import ast
 from ...tools import deprecated
 
 

nmigen/compat/fhdl/module.py

@@ -1,7 +1,7 @@
 from collections.abc import Iterable
 
 from ...tools import flatten, deprecated
-from ...fhdl import dsl
+from ...hdl import dsl
 
 
 __all__ = ["Module", "FinalizeError"]

nmigen/compat/fhdl/specials.py

@@ -1,4 +1,4 @@
-from ...genlib.io import TSTriple as NativeTSTriple
+from ...lib.io import TSTriple as NativeTSTriple
 
 
 __all__ = ["TSTriple"]

nmigen/compat/fhdl/structure.py

@@ -1,9 +1,9 @@
 from collections import OrderedDict
 
 from ...tools import deprecated
-from ...fhdl import ast
-from ...fhdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal
-from ...fhdl.cd import ClockDomain
+from ...hdl import ast
+from ...hdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal
+from ...hdl.cd import ClockDomain
 
 
 __all__ = ["DUID", "wrap", "Mux", "Cat", "Replicate", "Constant", "C", "Signal", "ClockSignal",

nmigen/compat/genlib/cdc.py

@@ -1,4 +1,4 @@
-from ...genlib.cdc import MultiReg
+from ...lib.cdc import MultiReg
 
 
 __all__ = ["MultiReg"]

nmigen/compat/genlib/fsm.py

@@ -1,8 +1,8 @@
 import warnings
 from collections import OrderedDict
 
-from ...fhdl.xfrm import ValueTransformer, StatementTransformer
-from ...fhdl.ast import *
+from ...hdl.xfrm import ValueTransformer, StatementTransformer
+from ...hdl.ast import *
 from ..fhdl.module import CompatModule, CompatFinalizeError
 from ..fhdl.structure import If, Case
 

nmigen/lib/cdc.py

@@ -1,4 +1,4 @@
-from ..fhdl import *
+from .. import *
 
 
 __all__ = ["MultiReg"]

nmigen/lib/io.py

@@ -1,4 +1,4 @@
-from ..fhdl import *
+from .. import *
 
 
 __all__ = ["TSTriple"]

nmigen/test/test_fhdl_ast.py

@@ -1,4 +1,4 @@
-from ..fhdl.ast import *
+from ..hdl.ast import *
 from .tools import *
 
 

nmigen/test/test_fhdl_cd.py

@@ -1,4 +1,4 @@
-from ..fhdl.cd import *
+from ..hdl.cd import *
 from .tools import *
 
 

nmigen/test/test_fhdl_dsl.py

@@ -1,5 +1,5 @@
-from ..fhdl.ast import *
-from ..fhdl.dsl import *
+from ..hdl.ast import *
+from ..hdl.dsl import *
 from .tools import *
 
 

nmigen/test/test_fhdl_ir.py

@@ -1,6 +1,6 @@
-from ..fhdl.ast import *
-from ..fhdl.cd import *
-from ..fhdl.ir import *
+from ..hdl.ast import *
+from ..hdl.cd import *
+from ..hdl.ir import *
 from .tools import *
 
 

nmigen/test/test_fhdl_xfrm.py

@@ -1,7 +1,7 @@
-from ..fhdl.ast import *
-from ..fhdl.cd import *
-from ..fhdl.ir import *
-from ..fhdl.xfrm import *
+from ..hdl.ast import *
+from ..hdl.cd import *
+from ..hdl.ir import *
+from ..hdl.xfrm import *
 from .tools import *
 
 

nmigen/test/test_sim.py

@@ -1,6 +1,6 @@
 from .tools import *
-from ..fhdl.ast import *
-from ..fhdl.ir import *
+from ..hdl.ast import *
+from ..hdl.ir import *
 from ..back.pysim import *
 
 

nmigen/test/tools.py

@@ -3,7 +3,7 @@ import unittest
 import warnings
 from contextlib import contextmanager
 
-from ..fhdl.ast import *
+from ..hdl.ast import *
 
 
 __all__ = ["FHDLTestCase"]