Rename fhdl→hdl, genlib→lib.

nmigen/__init__.py

@@ -1,7 +1,7 @@
-from .fhdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
-from .fhdl.dsl import Module
-from .fhdl.cd import ClockDomain
-from .fhdl.ir import Fragment
-from .fhdl.xfrm import ResetInserter, CEInserter
+from .hdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
+from .hdl.dsl import Module
+from .hdl.cd import ClockDomain
+from .hdl.ir import Fragment
+from .hdl.xfrm import ResetInserter, CEInserter
 
-from .genlib.cdc import MultiReg
+from .lib.cdc import MultiReg

nmigen/back/pysim.py

@@ -5,8 +5,8 @@ from vcd import VCDWriter
 from vcd.gtkw import GTKWSave
 
 from ..tools import flatten
-from ..fhdl.ast import *
-from ..fhdl.xfrm import ValueTransformer, StatementTransformer
+from ..hdl.ast import *
+from ..hdl.xfrm import ValueTransformer, StatementTransformer
 
 
 __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]

nmigen/back/rtlil.py

@@ -3,7 +3,7 @@ import textwrap
 from collections import defaultdict, OrderedDict
 from contextlib import contextmanager
 
-from ..fhdl import ast, ir, xfrm
+from ..hdl import ast, ir, xfrm
 
 
 class _Namer:

nmigen/compat/fhdl/bitcontainer.py

@@ -1,5 +1,5 @@
 from ... import tools
-from ...fhdl import ast
+from ...hdl import ast
 from ...tools import deprecated
 
 

nmigen/compat/fhdl/module.py

@@ -1,7 +1,7 @@
 from collections.abc import Iterable
 
 from ...tools import flatten, deprecated
-from ...fhdl import dsl
+from ...hdl import dsl
 
 
 __all__ = ["Module", "FinalizeError"]

nmigen/compat/fhdl/specials.py

@@ -1,4 +1,4 @@
-from ...genlib.io import TSTriple as NativeTSTriple
+from ...lib.io import TSTriple as NativeTSTriple
 
 
 __all__ = ["TSTriple"]

nmigen/compat/fhdl/structure.py

@@ -1,9 +1,9 @@
 from collections import OrderedDict
 
 from ...tools import deprecated
-from ...fhdl import ast
-from ...fhdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal
-from ...fhdl.cd import ClockDomain
+from ...hdl import ast
+from ...hdl.ast import DUID, Value, Signal, Mux, Cat, Repl, Const, C, ClockSignal, ResetSignal
+from ...hdl.cd import ClockDomain
 
 
 __all__ = ["DUID", "wrap", "Mux", "Cat", "Replicate", "Constant", "C", "Signal", "ClockSignal",

nmigen/compat/genlib/cdc.py

@@ -1,4 +1,4 @@
-from ...genlib.cdc import MultiReg
+from ...lib.cdc import MultiReg
 
 
 __all__ = ["MultiReg"]

nmigen/compat/genlib/fsm.py

@@ -1,8 +1,8 @@
 import warnings
 from collections import OrderedDict
 
-from ...fhdl.xfrm import ValueTransformer, StatementTransformer
-from ...fhdl.ast import *
+from ...hdl.xfrm import ValueTransformer, StatementTransformer
+from ...hdl.ast import *
 from ..fhdl.module import CompatModule, CompatFinalizeError
 from ..fhdl.structure import If, Case
 

nmigen/lib/cdc.py

@@ -1,4 +1,4 @@
-from ..fhdl import *
+from .. import *
 
 
 __all__ = ["MultiReg"]

nmigen/lib/io.py

@@ -1,4 +1,4 @@
-from ..fhdl import *
+from .. import *
 
 
 __all__ = ["TSTriple"]

nmigen/test/test_fhdl_ast.py

@@ -1,4 +1,4 @@
-from ..fhdl.ast import *
+from ..hdl.ast import *
 from .tools import *
 
 

nmigen/test/test_fhdl_cd.py

@@ -1,4 +1,4 @@
-from ..fhdl.cd import *
+from ..hdl.cd import *
 from .tools import *
 
 

nmigen/test/test_fhdl_dsl.py

@@ -1,5 +1,5 @@
-from ..fhdl.ast import *
-from ..fhdl.dsl import *
+from ..hdl.ast import *
+from ..hdl.dsl import *
 from .tools import *
 
 

nmigen/test/test_fhdl_ir.py

@@ -1,6 +1,6 @@
-from ..fhdl.ast import *
-from ..fhdl.cd import *
-from ..fhdl.ir import *
+from ..hdl.ast import *
+from ..hdl.cd import *
+from ..hdl.ir import *
 from .tools import *
 
 

nmigen/test/test_fhdl_xfrm.py

@@ -1,7 +1,7 @@
-from ..fhdl.ast import *
-from ..fhdl.cd import *
-from ..fhdl.ir import *
-from ..fhdl.xfrm import *
+from ..hdl.ast import *
+from ..hdl.cd import *
+from ..hdl.ir import *
+from ..hdl.xfrm import *
 from .tools import *
 
 

nmigen/test/test_sim.py

@@ -1,6 +1,6 @@
 from .tools import *
-from ..fhdl.ast import *
-from ..fhdl.ir import *
+from ..hdl.ast import *
+from ..hdl.ir import *
 from ..back.pysim import *
 
 

nmigen/test/tools.py

@@ -3,7 +3,7 @@ import unittest
 import warnings
 from contextlib import contextmanager
 
-from ..fhdl.ast import *
+from ..hdl.ast import *
 
 
 __all__ = ["FHDLTestCase"]