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hdl._ir: add caches for Matches and PriorityMatch cells.

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Wanda 2024-04-06 09:28:32 +02:00 • committed by Catherine
parent df589a54e0
commit 7936b87667
3 changed files with 78 additions and 93 deletions
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84
tests/test_hdl_ir.py
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@ -3247,8 +3247,6 @@ class SwitchTestCase(FHDLTestCase):
ClockSignal("b"), ResetSignal("b"),
ClockSignal("c"),
])
# TODO: inefficiency in NIR emitter:
# matches and priority_match duplicated between clock domains — add cache?
self.assertRepr(nl, """
(
(module 0 None ('top')
@ -3259,11 +3257,11 @@ class SwitchTestCase(FHDLTestCase):
(input 'b_clk' 0.13)
(input 'b_rst' 0.14)
(input 'c_clk' 0.15)
(output 'o1' 8.0:8)
(output 'o2' 12.0:8)
(output 'o3' 14.0:8)
(output 'o4' 16.0:8)
(output 'o5' 18.0:8)
(output 'o1' 4.0:8)
(output 'o2' 8.0:8)
(output 'o3' 10.0:8)
(output 'o4' 12.0:8)
(output 'o5' 14.0:8)
)
(cell 0 0 (top
(input 'i1' 2:10)
@ -3273,30 +3271,26 @@ class SwitchTestCase(FHDLTestCase):
(input 'b_clk' 13:14)
(input 'b_rst' 14:15)
(input 'c_clk' 15:16)
(output 'o1' 8.0:8)
(output 'o2' 12.0:8)
(output 'o3' 14.0:8)
(output 'o4' 16.0:8)
(output 'o5' 18.0:8)
(output 'o1' 4.0:8)
(output 'o2' 8.0:8)
(output 'o3' 10.0:8)
(output 'o4' 12.0:8)
(output 'o5' 14.0:8)
))
(cell 1 0 (matches 0.10 1))
(cell 2 0 (priority_match 1 1.0))
(cell 3 0 (matches 0.10 1))
(cell 4 0 (priority_match 1 3.0))
(cell 5 0 (matches 0.10 1))
(cell 3 0 (assignment_list 4.0:8 (2.0 0:8 0.2:10)))
(cell 4 0 (flipflop 3.0:8 0 pos 0.11 0))
(cell 5 0 (matches 0.12 1))
(cell 6 0 (priority_match 1 5.0))
(cell 7 0 (assignment_list 8.0:8 (2.0 0:8 0.2:10)))
(cell 8 0 (flipflop 7.0:8 0 pos 0.11 0))
(cell 9 0 (matches 0.12 1))
(cell 10 0 (priority_match 1 9.0))
(cell 11 0 (assignment_list 12.0:8 (2.0 0:8 0.2:10) (10.0 0:8 8'd123)))
(cell 12 0 (flipflop 11.0:8 123 pos 0.11 0))
(cell 13 0 (assignment_list 14.0:8 (4.0 0:8 0.2:10)))
(cell 14 0 (flipflop 13.0:8 45 pos 0.13 0))
(cell 15 0 (assignment_list 16.0:8 (4.0 0:8 0.2:10)))
(cell 16 0 (flipflop 15.0:8 67 pos 0.13 0.14))
(cell 17 0 (assignment_list 18.0:8 (6.0 0:8 0.2:10)))
(cell 18 0 (flipflop 17.0:8 89 neg 0.15 0))
(cell 7 0 (assignment_list 8.0:8 (2.0 0:8 0.2:10) (6.0 0:8 8'd123)))
(cell 8 0 (flipflop 7.0:8 123 pos 0.11 0))
(cell 9 0 (assignment_list 10.0:8 (2.0 0:8 0.2:10)))
(cell 10 0 (flipflop 9.0:8 45 pos 0.13 0))
(cell 11 0 (assignment_list 12.0:8 (2.0 0:8 0.2:10)))
(cell 12 0 (flipflop 11.0:8 67 pos 0.13 0.14))
(cell 13 0 (assignment_list 14.0:8 (2.0 0:8 0.2:10)))
(cell 14 0 (flipflop 13.0:8 89 neg 0.15 0))
)
""")
@ -3348,18 +3342,12 @@ class SwitchTestCase(FHDLTestCase):
(cell 4 0 (print 3.0 ((u 0.2:8 ''))))
(cell 5 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 6 0 (print 5.0 ((s 0.8:16 '') '\\n')))
(cell 7 0 (matches 0.16 1))
(cell 8 0 (priority_match 1 7.0))
(cell 9 0 (assignment_list 1'd0 (8.0 0:1 1'd1)))
(cell 10 0 (print 9.0 pos 0.17 ((u 0.2:8 '') ' ' (s 0.8:16 '') '\\n')))
(cell 11 0 (matches 0.16 1))
(cell 12 0 (priority_match 1 11.0))
(cell 13 0 (assignment_list 1'd0 (12.0 0:1 1'd1)))
(cell 14 0 (print 13.0 pos 0.19 ('values: ' (u 0.2:8 '02x') ', ' (s 0.8:16 '+d') '\\n')))
(cell 15 0 (matches 0.16 1))
(cell 16 0 (priority_match 1 15.0))
(cell 17 0 (assignment_list 1'd0 (16.0 0:1 1'd1)))
(cell 18 0 (print 17.0 neg 0.21 ('meow\\n')))
(cell 7 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 8 0 (print 7.0 pos 0.17 ((u 0.2:8 '') ' ' (s 0.8:16 '') '\\n')))
(cell 9 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 10 0 (print 9.0 pos 0.19 ('values: ' (u 0.2:8 '02x') ', ' (s 0.8:16 '+d') '\\n')))
(cell 11 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 12 0 (print 11.0 neg 0.21 ('meow\\n')))
)
""")
@ -3409,18 +3397,12 @@ class SwitchTestCase(FHDLTestCase):
(cell 7 0 (b 0.2:8))
(cell 8 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 9 0 (cover 7.0 8.0 ('d')))
(cell 10 0 (matches 0.7 1))
(cell 11 0 (priority_match 1 10.0))
(cell 12 0 (assignment_list 1'd0 (11.0 0:1 1'd1)))
(cell 13 0 (assert 0.4 12.0 pos 0.8 None))
(cell 14 0 (matches 0.7 1))
(cell 15 0 (priority_match 1 14.0))
(cell 16 0 (assignment_list 1'd0 (15.0 0:1 1'd1)))
(cell 17 0 (assume 0.5 16.0 pos 0.10 ('value: ' (u 0.2:8 ''))))
(cell 18 0 (matches 0.7 1))
(cell 19 0 (priority_match 1 18.0))
(cell 20 0 (assignment_list 1'd0 (19.0 0:1 1'd1)))
(cell 21 0 (cover 0.6 20.0 neg 0.12 ('c')))
(cell 10 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 11 0 (assert 0.4 10.0 pos 0.8 None))
(cell 12 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 13 0 (assume 0.5 12.0 pos 0.10 ('value: ' (u 0.2:8 ''))))
(cell 14 0 (assignment_list 1'd0 (2.0 0:1 1'd1)))
(cell 15 0 (cover 0.6 14.0 neg 0.12 ('c')))
)
""")