examples: update for newer API.

examples/arst.py

@@ -16,6 +16,6 @@ class ClockDivisor:
 
 if __name__ == "__main__":
     ctr = ClockDivisor(factor=16)
-    frag = ctr.elaborate(platform=None)
-    frag.add_domains(ClockDomain("sync", async_reset=True))
-    main(frag, ports=[ctr.o])
+    m = ctr.elaborate(platform=None)
+    m.domains += ClockDomain("sync", async_reset=True)
+    main(m, ports=[ctr.o])

examples/cdc.py

@@ -7,4 +7,4 @@ m = Module()
 m.submodules += MultiReg(i, o)
 
 if __name__ == "__main__":
-    main(m.lower(platform=None), ports=[i, o])
+    main(m, ports=[i, o])

examples/ctr_ce.py

@@ -16,12 +16,10 @@ class Counter:
 
 
 ctr = Counter(width=16)
-frag = ctr.elaborate(platform=None)
 
-# print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
-print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
+print(verilog.convert(ctr, ports=[ctr.o, ctr.ce]))
 
-with pysim.Simulator(frag,
+with pysim.Simulator(ctr,
         vcd_file=open("ctrl.vcd", "w"),
         gtkw_file=open("ctrl.gtkw", "w"),
         traces=[ctr.ce, ctr.v, ctr.o]) as sim:

examples/por.py

@@ -16,4 +16,4 @@ m.d.comb += [
 ]
 
 if __name__ == "__main__":
-    main(m.lower(platform=None), ports=[cd_por.clk])
+    main(m, ports=[cd_por.clk])

examples/tbuf.py

@@ -9,4 +9,4 @@ m = Module()
 m.submodules += pin_t.get_tristate(pin)
 
 if __name__ == "__main__":
-    main(m.lower(platform=None), ports=[pin, pin_t.oe, pin_t.i, pin_t.o])
+    main(m, ports=[pin, pin_t.oe, pin_t.i, pin_t.o])