back.pysim: fix behavior of initial cycle for sync processes.

The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.

nmigen/test/test_sim.py

@@ -279,9 +279,6 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
         with self.assertSimulation(self.m) as sim:
             sim.add_clock(1e-6, domain="sync")
             def process():
-                self.assertEqual((yield self.count), 4)
-                self.assertEqual((yield self.sync.clk), 0)
-                yield
                 self.assertEqual((yield self.count), 4)
                 self.assertEqual((yield self.sync.clk), 1)
                 yield