parent
7e2b72826f
commit
7c161957bf
2 changed files with 10 additions and 1 deletions
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@ -242,6 +242,12 @@ class ResourceTestCase(FHDLTestCase):
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" (subsignal rx (pins i A1))"
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" (attrs IOSTANDARD='LVCMOS33'))")
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def test_number_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Resource number must be an integer, not \(pins o 1\)$"):
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# number omitted by accident
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Resource("led", Pins("1", dir="o"))
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def test_family(self):
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ios = [Subsignal("clk", Pins("A0", dir="o"))]
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r1 = Resource.family(0, default_name="spi", ios=ios)
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