parent
7e2b72826f
commit
7c161957bf
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@ -197,8 +197,11 @@ class Resource(Subsignal):
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return cls(name_or_number + name_suffix, number, *ios)
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return cls(name_or_number + name_suffix, number, *ios)
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def __init__(self, name, number, *args):
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def __init__(self, name, number, *args):
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super().__init__(name, *args)
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if not isinstance(number, int):
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raise TypeError("Resource number must be an integer, not {!r}"
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.format(number))
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super().__init__(name, *args)
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self.number = number
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self.number = number
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def __repr__(self):
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def __repr__(self):
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@ -242,6 +242,12 @@ class ResourceTestCase(FHDLTestCase):
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" (subsignal rx (pins i A1))"
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" (subsignal rx (pins i A1))"
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" (attrs IOSTANDARD='LVCMOS33'))")
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" (attrs IOSTANDARD='LVCMOS33'))")
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def test_number_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Resource number must be an integer, not \(pins o 1\)$"):
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# number omitted by accident
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Resource("led", Pins("1", dir="o"))
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def test_family(self):
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def test_family(self):
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ios = [Subsignal("clk", Pins("A0", dir="o"))]
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ios = [Subsignal("clk", Pins("A0", dir="o"))]
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r1 = Resource.family(0, default_name="spi", ios=ios)
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r1 = Resource.family(0, default_name="spi", ios=ios)
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