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back.rtlil: extend shorter operand of a binop when matching sign.

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This is necessary because converting a large unsigned value to
a signed value of the same width may change its sign.

Fixes #271.
This commit is contained in:
whitequark 2019-11-18 10:39:55 +00:00
parent 834fe3c700
commit 7c322e562a
1 changed files with 1 additions and 0 deletions
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nmigen/back/rtlil.py
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@ -490,6 +490,7 @@ class _RHSValueCompiler(_ValueCompiler):
rhs_wire = self(rhs) rhs_wire = self(rhs)
else: else:
lhs_sign = rhs_sign = True lhs_sign = rhs_sign = True
lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign) lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign) rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
res_bits, res_sign = value.shape() res_bits, res_sign = value.shape()