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hdl.mem: fix naming of registers inside unnamed memories.

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Before this commit, `None` would leak into the vcd file with pysim.
This commit is contained in:
whitequark 2019-07-02 18:37:02 +00:00
parent 20553b1478
commit 7cc0b8cbf0
1 changed files with 2 additions and 1 deletions
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3
nmigen/hdl/mem.py
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@ -27,7 +27,8 @@ class Memory:
self._array = Array()
if simulate:
for addr in range(self.depth):
self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
self._array.append(Signal(self.width, name="{}({})"
.format(name or "memory", addr)))
self.init = init