Implement RFC 15: Lifting shape-castable objects.
See amaranth-lang/rfcs#15 and #784. Note that this RFC breaks the existing syntax for initializing a view with a new signal. Instances of `View(layout)` *must* be changed to `Signal(layout)`.
This commit is contained in:
Catherine
parent
e9975587bf
commit
7d99981d57
5 changed files with 149 additions and 199 deletions
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@ -145,8 +145,11 @@ class MockShapeCastable(ShapeCastable):
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def as_shape(self):
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return self.dest
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def const(self, obj):
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return Const(obj, self.dest)
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def __call__(self, value):
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return value
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def const(self, init):
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return Const(init, self.dest)
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class ShapeCastableTestCase(FHDLTestCase):
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@ -1004,6 +1007,9 @@ class SignalTestCase(FHDLTestCase):
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def as_shape(self):
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return unsigned(8)
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def __call__(self, value):
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return value
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def const(self, init):
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return int(init, 16)
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@ -16,6 +16,9 @@ class MockShapeCastable(ShapeCastable):
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def as_shape(self):
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return self.shape
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def __call__(self, value):
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return value
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def const(self, init):
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return Const(init, self.shape)
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@ -172,6 +175,12 @@ class UnionLayoutTestCase(TestCase):
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r"^Union layout member shape must be a shape-castable object, not 1\.0$"):
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UnionLayout({"a": 1.0})
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def test_const_two_members_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^Initializer for at most one field can be provided for a union layout "
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r"\(specified: a, b\)$"):
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UnionLayout({"a": 1, "b": 2}).const(dict(a=1, b=2))
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class ArrayLayoutTestCase(TestCase):
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def test_construct(self):
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@ -382,13 +391,13 @@ class LayoutTestCase(FHDLTestCase):
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self.assertRepr(sl.const(None), "(const 3'd0)")
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self.assertRepr(sl.const({"a": 0b1, "b": 0b10}), "(const 3'd5)")
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ul = UnionLayout({
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"a": unsigned(1),
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"b": unsigned(2)
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fl = FlexibleLayout(2, {
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"a": Field(unsigned(1), 0),
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"b": Field(unsigned(2), 0)
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})
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self.assertRepr(ul.const({"a": 0b11}), "(const 2'd1)")
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self.assertRepr(ul.const({"b": 0b10}), "(const 2'd2)")
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self.assertRepr(ul.const({"a": 0b1, "b": 0b10}), "(const 2'd2)")
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self.assertRepr(fl.const({"a": 0b11}), "(const 2'd1)")
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self.assertRepr(fl.const({"b": 0b10}), "(const 2'd2)")
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self.assertRepr(fl.const({"a": 0b1, "b": 0b10}), "(const 2'd2)")
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def test_const_wrong(self):
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sl = StructLayout({"f": unsigned(1)})
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@ -402,6 +411,9 @@ class LayoutTestCase(FHDLTestCase):
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def as_shape(self):
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return unsigned(8)
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def __call__(self, value):
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return value
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def const(self, init):
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return int(init, 16)
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@ -418,8 +430,8 @@ class LayoutTestCase(FHDLTestCase):
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"a": unsigned(1),
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"b": unsigned(2)
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})
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self.assertEqual(Signal(sl).reset, 0)
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self.assertEqual(Signal(sl, reset={"a": 0b1, "b": 0b10}).reset, 5)
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self.assertEqual(Signal(sl).as_value().reset, 0)
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self.assertEqual(Signal(sl, reset={"a": 0b1, "b": 0b10}).as_value().reset, 5)
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class ViewTestCase(FHDLTestCase):
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@ -431,41 +443,24 @@ class ViewTestCase(FHDLTestCase):
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self.assertRepr(v["b"], "(slice (sig s) 1:3)")
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def test_construct_signal(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}))
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v = Signal(StructLayout({"a": unsigned(1), "b": unsigned(2)}))
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cv = Value.cast(v)
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self.assertIsInstance(cv, Signal)
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self.assertEqual(cv.shape(), unsigned(3))
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self.assertEqual(cv.name, "v")
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def test_construct_signal_name(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), name="named")
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self.assertEqual(Value.cast(v).name, "named")
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def test_construct_signal_reset(self):
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v1 = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}),
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reset={"a": 0b1, "b": 0b10})
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v1 = Signal(StructLayout({"a": unsigned(1), "b": unsigned(2)}),
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reset={"a": 0b1, "b": 0b10})
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self.assertEqual(Value.cast(v1).reset, 0b101)
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v2 = View(StructLayout({"a": unsigned(1),
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v2 = Signal(StructLayout({"a": unsigned(1),
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"b": StructLayout({"x": unsigned(1), "y": unsigned(1)})}),
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reset={"a": 0b1, "b": {"x": 0b0, "y": 0b1}})
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reset={"a": 0b1, "b": {"x": 0b0, "y": 0b1}})
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self.assertEqual(Value.cast(v2).reset, 0b101)
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v3 = View(ArrayLayout(unsigned(2), 2),
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reset=[0b01, 0b10])
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v3 = Signal(ArrayLayout(unsigned(2), 2),
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reset=[0b01, 0b10])
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self.assertEqual(Value.cast(v3).reset, 0b1001)
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def test_construct_signal_reset_less(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), reset_less=True)
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self.assertEqual(Value.cast(v).reset_less, True)
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def test_construct_signal_attrs(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), attrs={"debug": 1})
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self.assertEqual(Value.cast(v).attrs, {"debug": 1})
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def test_construct_signal_decoder(self):
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decoder = lambda x: f"{x}"
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), decoder=decoder)
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self.assertEqual(Value.cast(v).decoder, decoder)
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def test_layout_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^View layout must be a layout, not <.+?>$"):
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@ -482,19 +477,8 @@ class ViewTestCase(FHDLTestCase):
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r"wide view layout$"):
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View(StructLayout({"a": unsigned(1)}), Signal(2))
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def test_signal_reset_wrong(self):
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with self.assertRaisesRegex(TypeError,
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r"^Reset value must be a constant initializer of StructLayout\({}\)$"):
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View(StructLayout({}), reset=0b1)
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def test_target_signal_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^View target cannot be provided at the same time as any of the Signal "
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r"constructor arguments \(name, reset, reset_less, attrs, decoder\)$"):
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View(StructLayout({}), Signal(), reset=0b1)
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def test_getitem(self):
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v = View(UnionLayout({
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v = Signal(UnionLayout({
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"a": unsigned(2),
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"s": StructLayout({
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"b": unsigned(1),
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@ -536,7 +520,7 @@ class ViewTestCase(FHDLTestCase):
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def const(self, init):
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return Const(init, 2)
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v = View(StructLayout({
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v = Signal(StructLayout({
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"f": Reverser()
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}))
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self.assertRepr(v.f, "(cat (slice (slice (sig v) 0:2) 1:2) "
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@ -553,7 +537,7 @@ class ViewTestCase(FHDLTestCase):
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def const(self, init):
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return Const(init, 2)
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v = View(StructLayout({
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v = Signal(StructLayout({
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"f": WrongCastable()
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}))
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with self.assertRaisesRegex(TypeError,
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@ -564,16 +548,16 @@ class ViewTestCase(FHDLTestCase):
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def test_index_wrong_missing(self):
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with self.assertRaisesRegex(KeyError,
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r"^'a'$"):
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View(StructLayout({}))["a"]
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Signal(StructLayout({}))["a"]
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def test_index_wrong_struct_dynamic(self):
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with self.assertRaisesRegex(TypeError,
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r"^Only views with array layout, not StructLayout\(\{\}\), may be indexed "
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r"with a value$"):
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View(StructLayout({}))[Signal(1)]
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Signal(StructLayout({}))[Signal(1)]
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def test_getattr(self):
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v = View(UnionLayout({
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v = Signal(UnionLayout({
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"a": unsigned(2),
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"s": StructLayout({
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"b": unsigned(1),
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@ -595,7 +579,7 @@ class ViewTestCase(FHDLTestCase):
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self.assertEqual(v.q.shape(), signed(1))
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def test_getattr_reserved(self):
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v = View(UnionLayout({
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v = Signal(UnionLayout({
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"_a": unsigned(2)
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}))
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self.assertRepr(v["_a"], "(slice (sig v) 0:2)")
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@ -604,13 +588,13 @@ class ViewTestCase(FHDLTestCase):
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with self.assertRaisesRegex(AttributeError,
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r"^View of \(sig \$signal\) does not have a field 'a'; "
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r"did you mean one of: 'b', 'c'\?$"):
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View(StructLayout({"b": unsigned(1), "c": signed(1)})).a
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Signal(StructLayout({"b": unsigned(1), "c": signed(1)})).a
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def test_attr_wrong_reserved(self):
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with self.assertRaisesRegex(AttributeError,
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r"^View of \(sig \$signal\) field '_c' has a reserved name "
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r"and may only be accessed by indexing$"):
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View(StructLayout({"_c": signed(1)}))._c
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Signal(StructLayout({"_c": signed(1)}))._c
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class StructTestCase(FHDLTestCase):
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@ -625,7 +609,7 @@ class StructTestCase(FHDLTestCase):
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"b": signed(3)
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}))
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v = S()
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v = Signal(S)
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self.assertEqual(Layout.of(v), S)
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self.assertEqual(Value.cast(v).shape(), Shape.cast(S))
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self.assertEqual(Value.cast(v).name, "v")
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@ -645,7 +629,7 @@ class StructTestCase(FHDLTestCase):
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self.assertEqual(Shape.cast(S), unsigned(9))
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v = S()
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v = Signal(S)
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self.assertIs(Layout.of(v), S)
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self.assertIsInstance(v, S)
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self.assertIs(Layout.of(v.b), R)
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@ -657,17 +641,6 @@ class StructTestCase(FHDLTestCase):
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self.assertRepr(v.b.q.r, "(s (slice (slice (slice (sig v) 1:9) 4:8) 0:2))")
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self.assertRepr(v.b.q.s, "(s (slice (slice (slice (sig v) 1:9) 4:8) 2:4))")
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def test_construct_signal_kwargs(self):
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decoder = lambda x: f"{x}"
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}),
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name="named", reset={"b": 0b1}, reset_less=True, attrs={"debug": 1}, decoder=decoder)
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s = Value.cast(v)
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self.assertEqual(s.name, "named")
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self.assertEqual(s.reset, 0b010)
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self.assertEqual(s.reset_less, True)
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self.assertEqual(s.attrs, {"debug": 1})
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self.assertEqual(s.decoder, decoder)
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def test_construct_reset(self):
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class S(Struct):
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p: 4
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@ -676,11 +649,11 @@ class StructTestCase(FHDLTestCase):
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with self.assertRaises(AttributeError):
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S.q
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v1 = S()
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v1 = Signal(S)
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self.assertEqual(v1.as_value().reset, 0b010000)
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v2 = S(reset=dict(p=0b0011))
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v2 = Signal(S, reset=dict(p=0b0011))
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self.assertEqual(v2.as_value().reset, 0b010011)
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v3 = S(reset=dict(p=0b0011, q=0b00))
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v3 = Signal(S, reset=dict(p=0b0011, q=0b00))
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self.assertEqual(v3.as_value().reset, 0b000011)
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def test_shape_undefined_wrong(self):
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@ -704,8 +677,8 @@ class StructTestCase(FHDLTestCase):
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a: 2
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b: 2
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self.assertEqual(Sb1().add().shape(), unsigned(2))
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self.assertEqual(Sb2().add().shape(), unsigned(3))
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self.assertEqual(Signal(Sb1).add().shape(), unsigned(2))
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self.assertEqual(Signal(Sb2).add().shape(), unsigned(3))
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def test_base_class_2(self):
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class Sb(Struct):
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@ -720,8 +693,8 @@ class StructTestCase(FHDLTestCase):
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def do(self):
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return self.a + self.b
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self.assertEqual(Sb1().do().shape(), unsigned(4))
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self.assertEqual(Sb2().do().shape(), unsigned(3))
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self.assertEqual(Signal(Sb1).do().shape(), unsigned(4))
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self.assertEqual(Signal(Sb2).do().shape(), unsigned(3))
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def test_layout_redefined_wrong(self):
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class Sb(Struct):
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@ -738,7 +711,7 @@ class StructTestCase(FHDLTestCase):
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b: int
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c: str = "x"
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self.assertEqual(Layout.of(S()), StructLayout({"a": unsigned(1)}))
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self.assertEqual(Layout.of(Signal(S)), StructLayout({"a": unsigned(1)}))
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self.assertEqual(S.__annotations__, {"b": int, "c": str})
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self.assertEqual(S.c, "x")
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@ -755,23 +728,12 @@ class UnionTestCase(FHDLTestCase):
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"b": signed(3)
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}))
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v = U()
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v = Signal(U)
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self.assertEqual(Layout.of(v), U)
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self.assertEqual(Value.cast(v).shape(), Shape.cast(U))
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self.assertRepr(v.a, "(slice (sig v) 0:1)")
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self.assertRepr(v.b, "(s (slice (sig v) 0:3))")
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def test_construct_signal_kwargs(self):
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decoder = lambda x: f"{x}"
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v = View(UnionLayout({"a": unsigned(1), "b": unsigned(2)}),
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name="named", reset={"b": 0b1}, reset_less=True, attrs={"debug": 1}, decoder=decoder)
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s = Value.cast(v)
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self.assertEqual(s.name, "named")
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self.assertEqual(s.reset, 0b01)
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self.assertEqual(s.reset_less, True)
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self.assertEqual(s.attrs, {"debug": 1})
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self.assertEqual(s.decoder, decoder)
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def test_define_reset_two_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^Reset value for at most one field can be provided for a union class "
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@ -785,18 +747,20 @@ class UnionTestCase(FHDLTestCase):
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a: unsigned(1)
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b: unsigned(2)
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with self.assertRaisesRegex(ValueError,
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r"^Reset value for at most one field can be provided for a union class "
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r"\(specified: a, b\)$"):
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U(reset=dict(a=1, b=2))
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with self.assertRaisesRegex(TypeError,
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r"^Reset value must be a constant initializer of <class '.+?\.U'>$") as cm:
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Signal(U, reset=dict(a=1, b=2))
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self.assertRegex(cm.exception.__cause__.message,
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r"^Initializer for at most one field can be provided for a union "
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r"class \(specified: a, b\)$")
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def test_construct_reset_override(self):
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class U(Union):
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a: unsigned(1) = 1
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b: unsigned(2)
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self.assertEqual(U().as_value().reset, 0b01)
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self.assertEqual(U(reset=dict(b=0b10)).as_value().reset, 0b10)
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self.assertEqual(Signal(U).as_value().reset, 0b01)
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self.assertEqual(Signal(U, reset=dict(b=0b10)).as_value().reset, 0b10)
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# Examples from https://github.com/amaranth-lang/amaranth/issues/693
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@ -817,7 +781,7 @@ class RFCExamplesTestCase(TestCase):
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self.assertEqual(Float32.as_shape().size, 32)
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flt_a = Float32()
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flt_a = Float32(Signal(32))
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flt_b = Float32(Const(0b00111110001000000000000000000000, 32))
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m1 = Module()
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@ -835,7 +799,7 @@ class RFCExamplesTestCase(TestCase):
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float: Float32
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int: signed(32)
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f_or_i = FloatOrInt32()
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f_or_i = Signal(FloatOrInt32)
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is_gt_1 = Signal()
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m2 = Module()
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m2.d.comb += [
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@ -857,10 +821,9 @@ class RFCExamplesTestCase(TestCase):
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"b": Float32
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})
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adder_op_storage = Signal(adder_op_layout)
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self.assertEqual(len(adder_op_storage), 65)
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adder_op = Signal(adder_op_layout)
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self.assertEqual(len(adder_op.as_value()), 65)
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adder_op = View(adder_op_layout, adder_op_storage)
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m3 = Module()
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m3.d.comb += [
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adder_op.eq(Op.SUB),
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@ -886,15 +849,10 @@ class RFCExamplesTestCase(TestCase):
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})
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self.assertEqual(layout1.size, 3)
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sig1 = Signal(layout1)
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self.assertEqual(sig1.shape(), unsigned(3))
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view1 = View(layout1, sig1)
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self.assertIs(Value.cast(view1), sig1)
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view2 = View(layout1)
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self.assertIsInstance(Value.cast(view2), Signal)
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self.assertEqual(Value.cast(view2).shape(), unsigned(3))
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view1 = Signal(layout1)
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self.assertIsInstance(view1, View)
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self.assertEqual(Layout.of(view1), layout1)
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self.assertEqual(view1.as_value().shape(), unsigned(3))
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m1 = Module()
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m1.d.comb += [
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@ -916,23 +874,20 @@ class RFCExamplesTestCase(TestCase):
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self.assertEqual(Shape.cast(SomeVariant), unsigned(3))
|
||||
|
||||
view3 = SomeVariant()
|
||||
self.assertIsInstance(Value.cast(view3), Signal)
|
||||
self.assertEqual(Value.cast(view3).shape(), unsigned(3))
|
||||
view2 = Signal(SomeVariant)
|
||||
self.assertIsInstance(Value.cast(view2), Signal)
|
||||
self.assertEqual(Value.cast(view2).shape(), unsigned(3))
|
||||
|
||||
m2 = Module()
|
||||
m2.submodules += m1
|
||||
m2.d.comb += [
|
||||
view3.kind.eq(Kind.ONE_SIGNED),
|
||||
view3.value.eq(view1.value)
|
||||
view2.kind.eq(Kind.ONE_SIGNED),
|
||||
view2.value.eq(view1.value)
|
||||
]
|
||||
|
||||
@self.simulate(m2)
|
||||
def check_m2():
|
||||
self.assertEqual((yield view3.as_value()), 0b010)
|
||||
|
||||
sig2 = Signal(SomeVariant)
|
||||
self.assertEqual(sig2.shape(), unsigned(3))
|
||||
self.assertEqual((yield view2.as_value()), 0b010)
|
||||
|
||||
layout2 = StructLayout({
|
||||
"ready": unsigned(1),
|
||||
|
|
@ -942,18 +897,4 @@ class RFCExamplesTestCase(TestCase):
|
|||
|
||||
self.assertEqual(layout1, Layout.cast(SomeVariant))
|
||||
|
||||
self.assertIs(SomeVariant, Layout.of(view3))
|
||||
|
||||
def test_rfc_example_3(self):
|
||||
class Stream8b10b(View):
|
||||
data: Signal
|
||||
ctrl: Signal
|
||||
|
||||
def __init__(self, value=None, *, width: int):
|
||||
super().__init__(StructLayout({
|
||||
"data": unsigned(8 * width),
|
||||
"ctrl": unsigned(width)
|
||||
}), value)
|
||||
|
||||
self.assertEqual(len(Stream8b10b(width=1).data), 8)
|
||||
self.assertEqual(len(Stream8b10b(width=4).data), 32)
|
||||
self.assertIs(SomeVariant, Layout.of(view2))
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue