Implement RFC 15: Lifting shape-castable objects.
See amaranth-lang/rfcs#15 and #784. Note that this RFC breaks the existing syntax for initializing a view with a new signal. Instances of `View(layout)` *must* be changed to `Signal(layout)`.
This commit is contained in:
Catherine
parent
e9975587bf
commit
7d99981d57
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@ -1,4 +1,5 @@
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from abc import ABCMeta, abstractmethod
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import inspect
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import warnings
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import functools
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from collections import OrderedDict
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@ -45,6 +46,9 @@ class ShapeCastable:
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if not hasattr(cls, "as_shape"):
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raise TypeError(f"Class '{cls.__name__}' deriving from `ShapeCastable` must override "
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f"the `as_shape` method")
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if not (hasattr(cls, "__call__") and inspect.isfunction(cls.__call__)):
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raise TypeError(f"Class '{cls.__name__}' deriving from `ShapeCastable` must override "
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f"the `__call__` method")
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if not hasattr(cls, "const"):
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raise TypeError(f"Class '{cls.__name__}' deriving from `ShapeCastable` must override "
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f"the `const` method")
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@ -949,8 +953,16 @@ class Repl(Value):
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return "(repl {!r} {})".format(self.value, self.count)
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class _SignalMeta(ABCMeta):
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def __call__(cls, shape=None, src_loc_at=0, **kwargs):
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signal = super().__call__(shape, **kwargs, src_loc_at=src_loc_at + 1)
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if isinstance(shape, ShapeCastable):
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return shape(signal)
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return signal
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# @final
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class Signal(Value, DUID):
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class Signal(Value, DUID, metaclass=_SignalMeta):
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"""A varying integer value.
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Parameters
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@ -390,6 +390,13 @@ class UnionLayout(Layout):
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"""
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return max((field.width for field in self._fields.values()), default=0)
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def const(self, init):
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if init is not None and len(init) > 1:
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raise ValueError("Initializer for at most one field can be provided for "
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"a union layout (specified: {})"
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.format(", ".join(init.keys())))
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return super().const(init)
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def __repr__(self):
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return f"UnionLayout({self.members!r})"
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@ -609,19 +616,12 @@ class View(ValueCastable):
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classes provided in this module are subclasses of :class:`View` that also provide a concise way
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to define a layout.
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"""
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def __init__(self, layout, target=None, *, name=None, reset=None, reset_less=None,
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attrs=None, decoder=None, src_loc_at=0):
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def __init__(self, layout, target):
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try:
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cast_layout = Layout.cast(layout)
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except TypeError as e:
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raise TypeError("View layout must be a layout, not {!r}"
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.format(layout)) from e
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if target is not None:
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if (name is not None or reset is not None or reset_less is not None or
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attrs is not None or decoder is not None):
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raise ValueError("View target cannot be provided at the same time as any of "
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"the Signal constructor arguments (name, reset, reset_less, "
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"attrs, decoder)")
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try:
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cast_target = Value.cast(target)
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except TypeError as e:
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@ -631,11 +631,6 @@ class View(ValueCastable):
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raise ValueError("View target is {} bit(s) wide, which is not compatible with "
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"the {} bit(s) wide view layout"
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.format(len(cast_target), cast_layout.size))
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else:
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if reset_less is None:
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reset_less = False
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cast_target = Signal(layout, name=name, reset=reset, reset_less=reset_less,
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attrs=attrs, decoder=decoder, src_loc_at=src_loc_at + 1)
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self.__orig_layout = layout
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self.__layout = cast_layout
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self.__target = cast_target
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@ -753,7 +748,7 @@ class _AggregateMeta(ShapeCastable, type):
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# This is a leaf class with its own layout. It is shape-castable and can
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# be instantiated. It can also be subclassed, and used to share layout and behavior.
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layout = dict()
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reset = dict()
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default = dict()
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for name in {**namespace["__annotations__"]}:
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try:
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Shape.cast(namespace["__annotations__"][name])
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@ -762,15 +757,15 @@ class _AggregateMeta(ShapeCastable, type):
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continue
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layout[name] = namespace["__annotations__"].pop(name)
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if name in namespace:
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reset[name] = namespace.pop(name)
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default[name] = namespace.pop(name)
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cls = type.__new__(metacls, name, bases, namespace)
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if cls.__layout_cls is UnionLayout:
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if len(reset) > 1:
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if len(default) > 1:
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raise ValueError("Reset value for at most one field can be provided for "
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"a union class (specified: {})"
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.format(", ".join(reset.keys())))
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.format(", ".join(default.keys())))
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cls.__layout = cls.__layout_cls(layout)
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cls.__reset = reset
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cls.__default = default
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return cls
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else:
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# This is a class that has a base class with a layout and annotations. Such a class
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@ -785,28 +780,24 @@ class _AggregateMeta(ShapeCastable, type):
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.format(cls.__module__, cls.__qualname__))
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return cls.__layout
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def __call__(cls, target):
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# This method exists to pass the override check done by ShapeCastable.
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return super().__call__(cls, target)
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def const(cls, init):
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return cls.as_shape().const(init)
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class _Aggregate(View, metaclass=_AggregateMeta):
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def __init__(self, target=None, *, name=None, reset=None, reset_less=None,
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attrs=None, decoder=None, src_loc_at=0):
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if self.__class__._AggregateMeta__layout_cls is UnionLayout:
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if reset is not None and len(reset) > 1:
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raise ValueError("Reset value for at most one field can be provided for "
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if cls.__layout_cls is UnionLayout:
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if init is not None and len(init) > 1:
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raise ValueError("Initializer for at most one field can be provided for "
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"a union class (specified: {})"
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.format(", ".join(reset.keys())))
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if target is None and hasattr(self.__class__, "_AggregateMeta__reset"):
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if reset is None:
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reset = self.__class__._AggregateMeta__reset
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elif self.__class__._AggregateMeta__layout_cls is not UnionLayout:
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reset = {**self.__class__._AggregateMeta__reset, **reset}
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super().__init__(self.__class__, target, name=name, reset=reset, reset_less=reset_less,
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attrs=attrs, decoder=decoder, src_loc_at=src_loc_at + 1)
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.format(", ".join(init.keys())))
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return cls.as_shape().const(init or cls.__default)
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else:
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fields = cls.__default.copy()
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fields.update(init or {})
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return cls.as_shape().const(fields)
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class Struct(_Aggregate):
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class Struct(View, metaclass=_AggregateMeta):
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"""Structures defined with annotations.
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The :class:`Struct` base class is a subclass of :class:`View` that provides a concise way
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@ -842,14 +833,14 @@ class Struct(_Aggregate):
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>>> IEEE754Single.as_shape()
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StructLayout({'fraction': 23, 'exponent': 8, 'sign': 1})
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>>> Signal(IEEE754Single).width
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>>> Signal(IEEE754Single).as_value().width
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32
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Instances of this class can be used where :ref:`values <lang-values>` are expected:
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.. doctest::
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>>> flt = IEEE754Single()
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>>> flt = Signal(IEEE754Single)
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>>> Signal(32).eq(flt)
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(eq (sig $signal) (sig flt))
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@ -866,11 +857,11 @@ class Struct(_Aggregate):
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.. doctest::
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>>> hex(IEEE754Single().as_value().reset)
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>>> hex(Signal(IEEE754Single).as_value().reset)
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'0x3f800000'
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>>> hex(IEEE754Single(reset={'sign': 1}).as_value().reset)
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>>> hex(Signal(IEEE754Single, reset={'sign': 1}).as_value().reset)
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'0xbf800000'
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>>> hex(IEEE754Single(reset={'exponent': 0}).as_value().reset)
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>>> hex(Signal(IEEE754Single, reset={'exponent': 0}).as_value().reset)
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'0x0'
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Classes inheriting from :class:`Struct` can be used as base classes. The only restrictions
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@ -903,15 +894,15 @@ class Struct(_Aggregate):
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Traceback (most recent call last):
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...
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TypeError: Aggregate class 'HasChecksum' does not have a defined shape
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>>> bare = BareHeader(); bare.checksum()
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>>> bare = Signal(BareHeader); bare.checksum()
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(+ (+ (+ (const 1'd0) (slice (sig bare) 0:8)) (slice (sig bare) 8:16)) (slice (sig bare) 16:24))
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>>> param = HeaderWithParam(); param.checksum()
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>>> param = Signal(HeaderWithParam); param.checksum()
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(+ (+ (+ (+ (const 1'd0) (slice (sig param) 0:8)) (slice (sig param) 8:16)) (slice (sig param) 16:24)) (slice (sig param) 24:32))
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"""
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_AggregateMeta__layout_cls = StructLayout
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class Union(_Aggregate):
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class Union(View, metaclass=_AggregateMeta):
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"""Unions defined with annotations.
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The :class:`Union` base class is a subclass of :class:`View` that provides a concise way
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@ -931,9 +922,9 @@ class Union(_Aggregate):
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.. doctest::
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>>> VarInt().as_value().reset
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>>> Signal(VarInt).as_value().reset
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256
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>>> VarInt(reset={'int8': 10}).as_value().reset
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>>> Signal(VarInt, reset={'int8': 10}).as_value().reset
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10
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"""
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_AggregateMeta__layout_cls = UnionLayout
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@ -56,7 +56,7 @@ While this implementation works, it is repetitive, error-prone, hard to read, an
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"blue": 5
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})
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i_color = data.View(rgb565_layout)
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i_color = Signal(rgb565_layout)
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o_gray = Signal(8)
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m.d.comb += o_gray.eq((i_color.red + i_color.green + i_color.blue) << 1)
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@ -82,7 +82,7 @@ For example, consider a module that processes RGB pixels in groups of up to four
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"valid": 4
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})
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i_stream = data.View(input_layout)
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i_stream = Signal(input_layout)
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r_accum = Signal(32)
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m.d.sync += r_accum.eq(
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@ -120,7 +120,7 @@ In case the data has related operations or transformations, :class:`View` can be
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.. testcode::
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class RGBPixelLayout(data.StructLayout):
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class RGBLayout(data.StructLayout):
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def __init__(self, r_bits, g_bits, b_bits):
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super().__init__({
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"red": unsigned(r_bits),
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@ -129,20 +129,20 @@ In case the data has related operations or transformations, :class:`View` can be
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})
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def __call__(self, value):
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return RGBPixelView(self, value)
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return RGBView(self, value)
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class RGBPixelView(data.View):
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class RGBView(data.View):
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def brightness(self):
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return (self.red + self.green + self.blue)[-8:]
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Here, the ``RGBLayout`` class itself is :ref:`shape-castable <lang-shapecasting>` and can be used anywhere a shape is accepted:
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Here, the ``RGBLayout`` class itself is :ref:`shape-castable <lang-shapecasting>` and can be used anywhere a shape is accepted. When a :class:`Signal` is constructed with this layout, the returned value is wrapped in an ``RGBView``:
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.. doctest::
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>>> pixel = Signal(RGBPixelLayout(5, 6, 5))
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>>> len(pixel)
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>>> pixel = Signal(RGBLayout(5, 6, 5))
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>>> len(pixel.as_value())
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16
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>>> RGBPixelView(RGBPixelLayout(5, 6, 5), pixel).red
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>>> pixel.red
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(slice (sig pixel) 0:5)
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In case the data format is static, :class:`Struct` (or :class:`Union`) can be subclassed instead of :class:`View`, to reduce the amount of boilerplate needed:
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@ -189,7 +189,7 @@ One module could submit a command with:
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.. testcode::
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cmd = Command()
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cmd = Signal(Command)
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m.d.comb += [
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cmd.valid.eq(1),
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@ -145,8 +145,11 @@ class MockShapeCastable(ShapeCastable):
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def as_shape(self):
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return self.dest
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def const(self, obj):
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return Const(obj, self.dest)
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def __call__(self, value):
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return value
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def const(self, init):
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return Const(init, self.dest)
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class ShapeCastableTestCase(FHDLTestCase):
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@ -1004,6 +1007,9 @@ class SignalTestCase(FHDLTestCase):
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def as_shape(self):
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return unsigned(8)
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def __call__(self, value):
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return value
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def const(self, init):
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return int(init, 16)
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@ -16,6 +16,9 @@ class MockShapeCastable(ShapeCastable):
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def as_shape(self):
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return self.shape
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def __call__(self, value):
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return value
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def const(self, init):
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return Const(init, self.shape)
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@ -172,6 +175,12 @@ class UnionLayoutTestCase(TestCase):
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r"^Union layout member shape must be a shape-castable object, not 1\.0$"):
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UnionLayout({"a": 1.0})
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def test_const_two_members_wrong(self):
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with self.assertRaisesRegex(ValueError,
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r"^Initializer for at most one field can be provided for a union layout "
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r"\(specified: a, b\)$"):
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UnionLayout({"a": 1, "b": 2}).const(dict(a=1, b=2))
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class ArrayLayoutTestCase(TestCase):
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def test_construct(self):
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@ -382,13 +391,13 @@ class LayoutTestCase(FHDLTestCase):
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self.assertRepr(sl.const(None), "(const 3'd0)")
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self.assertRepr(sl.const({"a": 0b1, "b": 0b10}), "(const 3'd5)")
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ul = UnionLayout({
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"a": unsigned(1),
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"b": unsigned(2)
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fl = FlexibleLayout(2, {
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"a": Field(unsigned(1), 0),
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"b": Field(unsigned(2), 0)
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})
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self.assertRepr(ul.const({"a": 0b11}), "(const 2'd1)")
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self.assertRepr(ul.const({"b": 0b10}), "(const 2'd2)")
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self.assertRepr(ul.const({"a": 0b1, "b": 0b10}), "(const 2'd2)")
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self.assertRepr(fl.const({"a": 0b11}), "(const 2'd1)")
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self.assertRepr(fl.const({"b": 0b10}), "(const 2'd2)")
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self.assertRepr(fl.const({"a": 0b1, "b": 0b10}), "(const 2'd2)")
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def test_const_wrong(self):
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sl = StructLayout({"f": unsigned(1)})
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@ -402,6 +411,9 @@ class LayoutTestCase(FHDLTestCase):
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def as_shape(self):
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return unsigned(8)
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def __call__(self, value):
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return value
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def const(self, init):
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return int(init, 16)
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@ -418,8 +430,8 @@ class LayoutTestCase(FHDLTestCase):
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"a": unsigned(1),
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"b": unsigned(2)
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})
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self.assertEqual(Signal(sl).reset, 0)
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self.assertEqual(Signal(sl, reset={"a": 0b1, "b": 0b10}).reset, 5)
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self.assertEqual(Signal(sl).as_value().reset, 0)
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self.assertEqual(Signal(sl, reset={"a": 0b1, "b": 0b10}).as_value().reset, 5)
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class ViewTestCase(FHDLTestCase):
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@ -431,41 +443,24 @@ class ViewTestCase(FHDLTestCase):
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self.assertRepr(v["b"], "(slice (sig s) 1:3)")
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def test_construct_signal(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}))
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v = Signal(StructLayout({"a": unsigned(1), "b": unsigned(2)}))
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cv = Value.cast(v)
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self.assertIsInstance(cv, Signal)
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self.assertEqual(cv.shape(), unsigned(3))
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self.assertEqual(cv.name, "v")
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def test_construct_signal_name(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), name="named")
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self.assertEqual(Value.cast(v).name, "named")
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def test_construct_signal_reset(self):
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v1 = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}),
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v1 = Signal(StructLayout({"a": unsigned(1), "b": unsigned(2)}),
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reset={"a": 0b1, "b": 0b10})
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self.assertEqual(Value.cast(v1).reset, 0b101)
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v2 = View(StructLayout({"a": unsigned(1),
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v2 = Signal(StructLayout({"a": unsigned(1),
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"b": StructLayout({"x": unsigned(1), "y": unsigned(1)})}),
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reset={"a": 0b1, "b": {"x": 0b0, "y": 0b1}})
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self.assertEqual(Value.cast(v2).reset, 0b101)
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v3 = View(ArrayLayout(unsigned(2), 2),
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v3 = Signal(ArrayLayout(unsigned(2), 2),
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reset=[0b01, 0b10])
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self.assertEqual(Value.cast(v3).reset, 0b1001)
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def test_construct_signal_reset_less(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), reset_less=True)
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self.assertEqual(Value.cast(v).reset_less, True)
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def test_construct_signal_attrs(self):
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), attrs={"debug": 1})
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self.assertEqual(Value.cast(v).attrs, {"debug": 1})
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def test_construct_signal_decoder(self):
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decoder = lambda x: f"{x}"
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v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}), decoder=decoder)
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self.assertEqual(Value.cast(v).decoder, decoder)
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|
||||
def test_layout_wrong(self):
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^View layout must be a layout, not <.+?>$"):
|
||||
|
|
@ -482,19 +477,8 @@ class ViewTestCase(FHDLTestCase):
|
|||
r"wide view layout$"):
|
||||
View(StructLayout({"a": unsigned(1)}), Signal(2))
|
||||
|
||||
def test_signal_reset_wrong(self):
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Reset value must be a constant initializer of StructLayout\({}\)$"):
|
||||
View(StructLayout({}), reset=0b1)
|
||||
|
||||
def test_target_signal_wrong(self):
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^View target cannot be provided at the same time as any of the Signal "
|
||||
r"constructor arguments \(name, reset, reset_less, attrs, decoder\)$"):
|
||||
View(StructLayout({}), Signal(), reset=0b1)
|
||||
|
||||
def test_getitem(self):
|
||||
v = View(UnionLayout({
|
||||
v = Signal(UnionLayout({
|
||||
"a": unsigned(2),
|
||||
"s": StructLayout({
|
||||
"b": unsigned(1),
|
||||
|
|
@ -536,7 +520,7 @@ class ViewTestCase(FHDLTestCase):
|
|||
def const(self, init):
|
||||
return Const(init, 2)
|
||||
|
||||
v = View(StructLayout({
|
||||
v = Signal(StructLayout({
|
||||
"f": Reverser()
|
||||
}))
|
||||
self.assertRepr(v.f, "(cat (slice (slice (sig v) 0:2) 1:2) "
|
||||
|
|
@ -553,7 +537,7 @@ class ViewTestCase(FHDLTestCase):
|
|||
def const(self, init):
|
||||
return Const(init, 2)
|
||||
|
||||
v = View(StructLayout({
|
||||
v = Signal(StructLayout({
|
||||
"f": WrongCastable()
|
||||
}))
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
|
|
@ -564,16 +548,16 @@ class ViewTestCase(FHDLTestCase):
|
|||
def test_index_wrong_missing(self):
|
||||
with self.assertRaisesRegex(KeyError,
|
||||
r"^'a'$"):
|
||||
View(StructLayout({}))["a"]
|
||||
Signal(StructLayout({}))["a"]
|
||||
|
||||
def test_index_wrong_struct_dynamic(self):
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Only views with array layout, not StructLayout\(\{\}\), may be indexed "
|
||||
r"with a value$"):
|
||||
View(StructLayout({}))[Signal(1)]
|
||||
Signal(StructLayout({}))[Signal(1)]
|
||||
|
||||
def test_getattr(self):
|
||||
v = View(UnionLayout({
|
||||
v = Signal(UnionLayout({
|
||||
"a": unsigned(2),
|
||||
"s": StructLayout({
|
||||
"b": unsigned(1),
|
||||
|
|
@ -595,7 +579,7 @@ class ViewTestCase(FHDLTestCase):
|
|||
self.assertEqual(v.q.shape(), signed(1))
|
||||
|
||||
def test_getattr_reserved(self):
|
||||
v = View(UnionLayout({
|
||||
v = Signal(UnionLayout({
|
||||
"_a": unsigned(2)
|
||||
}))
|
||||
self.assertRepr(v["_a"], "(slice (sig v) 0:2)")
|
||||
|
|
@ -604,13 +588,13 @@ class ViewTestCase(FHDLTestCase):
|
|||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^View of \(sig \$signal\) does not have a field 'a'; "
|
||||
r"did you mean one of: 'b', 'c'\?$"):
|
||||
View(StructLayout({"b": unsigned(1), "c": signed(1)})).a
|
||||
Signal(StructLayout({"b": unsigned(1), "c": signed(1)})).a
|
||||
|
||||
def test_attr_wrong_reserved(self):
|
||||
with self.assertRaisesRegex(AttributeError,
|
||||
r"^View of \(sig \$signal\) field '_c' has a reserved name "
|
||||
r"and may only be accessed by indexing$"):
|
||||
View(StructLayout({"_c": signed(1)}))._c
|
||||
Signal(StructLayout({"_c": signed(1)}))._c
|
||||
|
||||
|
||||
class StructTestCase(FHDLTestCase):
|
||||
|
|
@ -625,7 +609,7 @@ class StructTestCase(FHDLTestCase):
|
|||
"b": signed(3)
|
||||
}))
|
||||
|
||||
v = S()
|
||||
v = Signal(S)
|
||||
self.assertEqual(Layout.of(v), S)
|
||||
self.assertEqual(Value.cast(v).shape(), Shape.cast(S))
|
||||
self.assertEqual(Value.cast(v).name, "v")
|
||||
|
|
@ -645,7 +629,7 @@ class StructTestCase(FHDLTestCase):
|
|||
|
||||
self.assertEqual(Shape.cast(S), unsigned(9))
|
||||
|
||||
v = S()
|
||||
v = Signal(S)
|
||||
self.assertIs(Layout.of(v), S)
|
||||
self.assertIsInstance(v, S)
|
||||
self.assertIs(Layout.of(v.b), R)
|
||||
|
|
@ -657,17 +641,6 @@ class StructTestCase(FHDLTestCase):
|
|||
self.assertRepr(v.b.q.r, "(s (slice (slice (slice (sig v) 1:9) 4:8) 0:2))")
|
||||
self.assertRepr(v.b.q.s, "(s (slice (slice (slice (sig v) 1:9) 4:8) 2:4))")
|
||||
|
||||
def test_construct_signal_kwargs(self):
|
||||
decoder = lambda x: f"{x}"
|
||||
v = View(StructLayout({"a": unsigned(1), "b": unsigned(2)}),
|
||||
name="named", reset={"b": 0b1}, reset_less=True, attrs={"debug": 1}, decoder=decoder)
|
||||
s = Value.cast(v)
|
||||
self.assertEqual(s.name, "named")
|
||||
self.assertEqual(s.reset, 0b010)
|
||||
self.assertEqual(s.reset_less, True)
|
||||
self.assertEqual(s.attrs, {"debug": 1})
|
||||
self.assertEqual(s.decoder, decoder)
|
||||
|
||||
def test_construct_reset(self):
|
||||
class S(Struct):
|
||||
p: 4
|
||||
|
|
@ -676,11 +649,11 @@ class StructTestCase(FHDLTestCase):
|
|||
with self.assertRaises(AttributeError):
|
||||
S.q
|
||||
|
||||
v1 = S()
|
||||
v1 = Signal(S)
|
||||
self.assertEqual(v1.as_value().reset, 0b010000)
|
||||
v2 = S(reset=dict(p=0b0011))
|
||||
v2 = Signal(S, reset=dict(p=0b0011))
|
||||
self.assertEqual(v2.as_value().reset, 0b010011)
|
||||
v3 = S(reset=dict(p=0b0011, q=0b00))
|
||||
v3 = Signal(S, reset=dict(p=0b0011, q=0b00))
|
||||
self.assertEqual(v3.as_value().reset, 0b000011)
|
||||
|
||||
def test_shape_undefined_wrong(self):
|
||||
|
|
@ -704,8 +677,8 @@ class StructTestCase(FHDLTestCase):
|
|||
a: 2
|
||||
b: 2
|
||||
|
||||
self.assertEqual(Sb1().add().shape(), unsigned(2))
|
||||
self.assertEqual(Sb2().add().shape(), unsigned(3))
|
||||
self.assertEqual(Signal(Sb1).add().shape(), unsigned(2))
|
||||
self.assertEqual(Signal(Sb2).add().shape(), unsigned(3))
|
||||
|
||||
def test_base_class_2(self):
|
||||
class Sb(Struct):
|
||||
|
|
@ -720,8 +693,8 @@ class StructTestCase(FHDLTestCase):
|
|||
def do(self):
|
||||
return self.a + self.b
|
||||
|
||||
self.assertEqual(Sb1().do().shape(), unsigned(4))
|
||||
self.assertEqual(Sb2().do().shape(), unsigned(3))
|
||||
self.assertEqual(Signal(Sb1).do().shape(), unsigned(4))
|
||||
self.assertEqual(Signal(Sb2).do().shape(), unsigned(3))
|
||||
|
||||
def test_layout_redefined_wrong(self):
|
||||
class Sb(Struct):
|
||||
|
|
@ -738,7 +711,7 @@ class StructTestCase(FHDLTestCase):
|
|||
b: int
|
||||
c: str = "x"
|
||||
|
||||
self.assertEqual(Layout.of(S()), StructLayout({"a": unsigned(1)}))
|
||||
self.assertEqual(Layout.of(Signal(S)), StructLayout({"a": unsigned(1)}))
|
||||
self.assertEqual(S.__annotations__, {"b": int, "c": str})
|
||||
self.assertEqual(S.c, "x")
|
||||
|
||||
|
|
@ -755,23 +728,12 @@ class UnionTestCase(FHDLTestCase):
|
|||
"b": signed(3)
|
||||
}))
|
||||
|
||||
v = U()
|
||||
v = Signal(U)
|
||||
self.assertEqual(Layout.of(v), U)
|
||||
self.assertEqual(Value.cast(v).shape(), Shape.cast(U))
|
||||
self.assertRepr(v.a, "(slice (sig v) 0:1)")
|
||||
self.assertRepr(v.b, "(s (slice (sig v) 0:3))")
|
||||
|
||||
def test_construct_signal_kwargs(self):
|
||||
decoder = lambda x: f"{x}"
|
||||
v = View(UnionLayout({"a": unsigned(1), "b": unsigned(2)}),
|
||||
name="named", reset={"b": 0b1}, reset_less=True, attrs={"debug": 1}, decoder=decoder)
|
||||
s = Value.cast(v)
|
||||
self.assertEqual(s.name, "named")
|
||||
self.assertEqual(s.reset, 0b01)
|
||||
self.assertEqual(s.reset_less, True)
|
||||
self.assertEqual(s.attrs, {"debug": 1})
|
||||
self.assertEqual(s.decoder, decoder)
|
||||
|
||||
def test_define_reset_two_wrong(self):
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Reset value for at most one field can be provided for a union class "
|
||||
|
|
@ -785,18 +747,20 @@ class UnionTestCase(FHDLTestCase):
|
|||
a: unsigned(1)
|
||||
b: unsigned(2)
|
||||
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Reset value for at most one field can be provided for a union class "
|
||||
r"\(specified: a, b\)$"):
|
||||
U(reset=dict(a=1, b=2))
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Reset value must be a constant initializer of <class '.+?\.U'>$") as cm:
|
||||
Signal(U, reset=dict(a=1, b=2))
|
||||
self.assertRegex(cm.exception.__cause__.message,
|
||||
r"^Initializer for at most one field can be provided for a union "
|
||||
r"class \(specified: a, b\)$")
|
||||
|
||||
def test_construct_reset_override(self):
|
||||
class U(Union):
|
||||
a: unsigned(1) = 1
|
||||
b: unsigned(2)
|
||||
|
||||
self.assertEqual(U().as_value().reset, 0b01)
|
||||
self.assertEqual(U(reset=dict(b=0b10)).as_value().reset, 0b10)
|
||||
self.assertEqual(Signal(U).as_value().reset, 0b01)
|
||||
self.assertEqual(Signal(U, reset=dict(b=0b10)).as_value().reset, 0b10)
|
||||
|
||||
|
||||
# Examples from https://github.com/amaranth-lang/amaranth/issues/693
|
||||
|
|
@ -817,7 +781,7 @@ class RFCExamplesTestCase(TestCase):
|
|||
|
||||
self.assertEqual(Float32.as_shape().size, 32)
|
||||
|
||||
flt_a = Float32()
|
||||
flt_a = Float32(Signal(32))
|
||||
flt_b = Float32(Const(0b00111110001000000000000000000000, 32))
|
||||
|
||||
m1 = Module()
|
||||
|
|
@ -835,7 +799,7 @@ class RFCExamplesTestCase(TestCase):
|
|||
float: Float32
|
||||
int: signed(32)
|
||||
|
||||
f_or_i = FloatOrInt32()
|
||||
f_or_i = Signal(FloatOrInt32)
|
||||
is_gt_1 = Signal()
|
||||
m2 = Module()
|
||||
m2.d.comb += [
|
||||
|
|
@ -857,10 +821,9 @@ class RFCExamplesTestCase(TestCase):
|
|||
"b": Float32
|
||||
})
|
||||
|
||||
adder_op_storage = Signal(adder_op_layout)
|
||||
self.assertEqual(len(adder_op_storage), 65)
|
||||
adder_op = Signal(adder_op_layout)
|
||||
self.assertEqual(len(adder_op.as_value()), 65)
|
||||
|
||||
adder_op = View(adder_op_layout, adder_op_storage)
|
||||
m3 = Module()
|
||||
m3.d.comb += [
|
||||
adder_op.eq(Op.SUB),
|
||||
|
|
@ -886,15 +849,10 @@ class RFCExamplesTestCase(TestCase):
|
|||
})
|
||||
self.assertEqual(layout1.size, 3)
|
||||
|
||||
sig1 = Signal(layout1)
|
||||
self.assertEqual(sig1.shape(), unsigned(3))
|
||||
|
||||
view1 = View(layout1, sig1)
|
||||
self.assertIs(Value.cast(view1), sig1)
|
||||
|
||||
view2 = View(layout1)
|
||||
self.assertIsInstance(Value.cast(view2), Signal)
|
||||
self.assertEqual(Value.cast(view2).shape(), unsigned(3))
|
||||
view1 = Signal(layout1)
|
||||
self.assertIsInstance(view1, View)
|
||||
self.assertEqual(Layout.of(view1), layout1)
|
||||
self.assertEqual(view1.as_value().shape(), unsigned(3))
|
||||
|
||||
m1 = Module()
|
||||
m1.d.comb += [
|
||||
|
|
@ -916,23 +874,20 @@ class RFCExamplesTestCase(TestCase):
|
|||
|
||||
self.assertEqual(Shape.cast(SomeVariant), unsigned(3))
|
||||
|
||||
view3 = SomeVariant()
|
||||
self.assertIsInstance(Value.cast(view3), Signal)
|
||||
self.assertEqual(Value.cast(view3).shape(), unsigned(3))
|
||||
view2 = Signal(SomeVariant)
|
||||
self.assertIsInstance(Value.cast(view2), Signal)
|
||||
self.assertEqual(Value.cast(view2).shape(), unsigned(3))
|
||||
|
||||
m2 = Module()
|
||||
m2.submodules += m1
|
||||
m2.d.comb += [
|
||||
view3.kind.eq(Kind.ONE_SIGNED),
|
||||
view3.value.eq(view1.value)
|
||||
view2.kind.eq(Kind.ONE_SIGNED),
|
||||
view2.value.eq(view1.value)
|
||||
]
|
||||
|
||||
@self.simulate(m2)
|
||||
def check_m2():
|
||||
self.assertEqual((yield view3.as_value()), 0b010)
|
||||
|
||||
sig2 = Signal(SomeVariant)
|
||||
self.assertEqual(sig2.shape(), unsigned(3))
|
||||
self.assertEqual((yield view2.as_value()), 0b010)
|
||||
|
||||
layout2 = StructLayout({
|
||||
"ready": unsigned(1),
|
||||
|
|
@ -942,18 +897,4 @@ class RFCExamplesTestCase(TestCase):
|
|||
|
||||
self.assertEqual(layout1, Layout.cast(SomeVariant))
|
||||
|
||||
self.assertIs(SomeVariant, Layout.of(view3))
|
||||
|
||||
def test_rfc_example_3(self):
|
||||
class Stream8b10b(View):
|
||||
data: Signal
|
||||
ctrl: Signal
|
||||
|
||||
def __init__(self, value=None, *, width: int):
|
||||
super().__init__(StructLayout({
|
||||
"data": unsigned(8 * width),
|
||||
"ctrl": unsigned(width)
|
||||
}), value)
|
||||
|
||||
self.assertEqual(len(Stream8b10b(width=1).data), 8)
|
||||
self.assertEqual(len(Stream8b10b(width=4).data), 32)
|
||||
self.assertIs(SomeVariant, Layout.of(view2))
|
||||
|
|
|
|||
Loading…
Reference in a new issue