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sim.core: warn when driving a clock domain not in the simulation.

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Closes #566.
This commit is contained in:
whitequark 2021-12-11 13:22:24 +00:00
parent ac13a5b3c9
commit 7e2b72826f
2 changed files with 17 additions and 1 deletions
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9
tests/test_sim.py
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@ -851,3 +851,12 @@ class SimulatorRegressionTestCase(FHDLTestCase):
r"^Value defined at .+?/test_sim\.py:\d+ is 4294967327 bits wide, "
r"which is unlikely to simulate in reasonable time$"):
Simulator(dut)
def test_bug_566(self):
dut = Module()
dut.d.sync += Signal().eq(0)
sim = Simulator(dut)
with self.assertWarnsRegex(UserWarning,
r"^Adding a clock process that drives a clock domain object named 'sync', "
r"which is distinct from an identically named domain in the simulated design$"):
sim.add_clock(1e-6, domain=ClockDomain("sync"))