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vendor.intel: add Quartus support.

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Co-authored-by: Dan Ravensloft <dan.ravensloft@gmail.com>
This commit is contained in:
whitequark 2019-08-21 22:14:33 +00:00
parent 7dfd7fb12a
commit 8021e2dd76
3 changed files with 402 additions and 6 deletions
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5
nmigen/back/verilog.py
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@ -21,7 +21,7 @@ def _yosys_version():
return tuple(map(int, tag.split("."))), offset
def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False):
def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
version, offset = _yosys_version()
if version < (0, 9):
raise YosysError("Yosys %d.%d is not suppored", *version)
@ -47,10 +47,11 @@ proc_clean
memory_collect
attrmap {attr_map}
attrmap -modattr {attr_map}
write_verilog -norename
write_verilog -norename {write_verilog_opts}
""".format(rtlil_text,
prune="# " if version == (0, 9) and offset == 0 else "",
attr_map=" ".join(attr_map),
write_verilog_opts=" ".join(write_verilog_opts),
)
popen = subprocess.Popen([require_tool("yosys"), "-q", "-"],