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vendor.intel: fix output enable width for XDR=0 case.

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Fixes #297.
This commit is contained in:
schwigi 2020-01-09 11:09:35 +01:00 committed by whitequark
parent 63902dddb7
commit 8184efd612
1 changed files with 3 additions and 2 deletions
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5
nmigen/vendor/intel.py vendored
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@ -221,8 +221,9 @@ class IntelPlatform(TemplatedPlatform):
@staticmethod @staticmethod
def _get_oereg(m, pin): def _get_oereg(m, pin):
# altiobuf_ requires an output enable signal for each pin, but pin.oe is 1 bit wide.
if pin.xdr == 0: if pin.xdr == 0:
return pin.oe return Repl(pin.oe, pin.width)
elif pin.xdr in (1, 2): elif pin.xdr in (1, 2):
oe_reg = Signal(pin.width, name="{}_oe_reg".format(pin.name)) oe_reg = Signal(pin.width, name="{}_oe_reg".format(pin.name))
oe_reg.attrs["useioff"] = "1" oe_reg.attrs["useioff"] = "1"
@ -283,7 +284,7 @@ class IntelPlatform(TemplatedPlatform):
p_use_oe="TRUE", p_use_oe="TRUE",
i_datain=self._get_oreg(m, pin, invert), i_datain=self._get_oreg(m, pin, invert),
o_dataout=port, o_dataout=port,
i_oe=pin.oe, i_oe=self._get_oereg(m, pin)
) )
return m return m