back.rtlil: emit \src attributes for processes via Switch and Assign.

The locations are unfortunately not very precise, but they provide
some improvement over status quo.

nmigen/hdl/ast.py

@@ -178,7 +178,7 @@ class Value(metaclass=ABCMeta):
         Assign
             Assignment statement that can be used in combinatorial or synchronous context.
         """
-        return Assign(self, value)
+        return Assign(self, value, src_loc_at=1)
 
     @abstractmethod
     def shape(self):
@@ -975,7 +975,9 @@ class Statement:
 
 @final
 class Assign(Statement):
-    def __init__(self, lhs, rhs):
+    def __init__(self, lhs, rhs, src_loc_at=0):
+        self.src_loc = tracer.get_src_loc(src_loc_at)
+
         self.lhs = Value.wrap(lhs)
         self.rhs = Value.wrap(rhs)
 
@@ -1027,7 +1029,9 @@ class Assume(Property):
 
 # @final
 class Switch(Statement):
-    def __init__(self, test, cases):
+    def __init__(self, test, cases, src_loc_at=0):
+        self.src_loc = tracer.get_src_loc(src_loc_at)
+
         self.test  = Value.wrap(test)
         self.cases = OrderedDict()
         for keys, stmts in cases.items():

nmigen/hdl/dsl.py

@@ -304,6 +304,10 @@ class Module(_ModuleBuilderRoot, Elaboratable):
         raise SyntaxError("`m.next = <...>` is only permitted inside an FSM state")
 
     def _pop_ctrl(self):
+        # FIXME: the src_loc extraction unfortunately doesn't work very well here; src_loc_at=3 is
+        # correct, but the resulting src_loc points at the *last* line of the `with` block.
+        # Unfortunately, it is not clear how this can be fixed.
+
         name, data = self._ctrl_stack.pop()
 
         if name == "If":
@@ -323,12 +327,12 @@ class Module(_ModuleBuilderRoot, Elaboratable):
                     match = None
                 cases[match] = if_case
 
-            self._statements.append(Switch(Cat(tests), cases))
+            self._statements.append(Switch(Cat(tests), cases, src_loc_at=3))
 
         if name == "Switch":
             switch_test, switch_cases = data["test"], data["cases"]
 
-            self._statements.append(Switch(switch_test, switch_cases))
+            self._statements.append(Switch(switch_test, switch_cases, src_loc_at=3))
 
         if name == "FSM":
             fsm_signal, fsm_reset, fsm_encoding, fsm_decoding, fsm_states = \
@@ -342,7 +346,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
             fsm_decoding.update((n, s) for s, n in fsm_encoding.items())
             fsm_signal.decoder = lambda n: "{}/{}".format(fsm_decoding[n], n)
             self._statements.append(Switch(fsm_signal,
-                OrderedDict((fsm_encoding[name], stmts) for name, stmts in fsm_states.items())))
+                OrderedDict((fsm_encoding[name], stmts) for name, stmts in fsm_states.items()),
+                src_loc_at=3))
 
     def _add_statement(self, assigns, domain, depth, compat_mode=False):
         def domain_name(domain):

nmigen/hdl/xfrm.py

@@ -211,8 +211,8 @@ class StatementVisitor(metaclass=ABCMeta):
             new_stmt.src_loc = stmt.src_loc
         return new_stmt
 
-    def __call__(self, value):
-        return self.on_statement(value)
+    def __call__(self, stmt):
+        return self.on_statement(stmt)
 
 
 class StatementTransformer(StatementVisitor):