back.pysim: warn if simulation is not run.
This would have prevented 3ea35b85
.
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parent
92a96e1644
commit
849c649259
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@ -1,5 +1,6 @@
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import math
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import math
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import inspect
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import inspect
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import warnings
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from contextlib import contextmanager
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from contextlib import contextmanager
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from bitarray import bitarray
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from bitarray import bitarray
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from vcd import VCDWriter
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from vcd import VCDWriter
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@ -365,6 +366,8 @@ class Simulator:
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self._gtkw_file = gtkw_file
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self._gtkw_file = gtkw_file
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self._traces = traces
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self._traces = traces
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self._run_called = False
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while not isinstance(self._fragment, Fragment):
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while not isinstance(self._fragment, Fragment):
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self._fragment = self._fragment.get_fragment(platform=None)
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self._fragment = self._fragment.get_fragment(platform=None)
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@ -755,10 +758,14 @@ class Simulator:
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return False
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return False
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def run(self):
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def run(self):
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self._run_called = True
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while self.step():
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while self.step():
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pass
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pass
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def run_until(self, deadline, run_passive=False):
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def run_until(self, deadline, run_passive=False):
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self._run_called = True
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while self._timestamp < deadline:
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while self._timestamp < deadline:
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if not self.step(run_passive):
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if not self.step(run_passive):
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return False
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return False
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@ -766,6 +773,9 @@ class Simulator:
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return True
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return True
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def __exit__(self, *args):
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def __exit__(self, *args):
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if not self._run_called:
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warnings.warn("Simulation created, but not run", UserWarning)
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if self._vcd_writer:
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if self._vcd_writer:
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vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
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vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
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self._vcd_writer.close(vcd_timestamp)
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self._vcd_writer.close(vcd_timestamp)
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@ -530,3 +530,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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self.assertEqual((yield self.rdport.data), 0x33)
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self.assertEqual((yield self.rdport.data), 0x33)
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sim.add_clock(1e-6)
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sim.add_clock(1e-6)
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sim.add_process(process)
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sim.add_process(process)
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def test_wrong_not_run(self):
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with self.assertWarns(UserWarning,
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msg="Simulation created, but not run"):
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with Simulator(Fragment()) as sim:
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pass
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