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ClockDomain.{rst→reset}, for consistency with ResetInserter.

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nmigen.compat.ClockDomain would alias this, for Migen compatibility.
This commit is contained in:
whitequark 2018-12-12 09:49:02 +00:00
parent 4d3258013d
commit 851ed06769
4 changed files with 7 additions and 7 deletions
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4
examples/arst.py
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@ -17,5 +17,5 @@ class ClockDivisor:
sys = ClockDomain(async_reset=True)
ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys}))
# print(rtlil.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))