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ClockDomain.{rst→reset}, for consistency with ResetInserter.

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nmigen.compat.ClockDomain would alias this, for Migen compatibility.
This commit is contained in:
whitequark 2018-12-12 09:49:02 +00:00
parent 4d3258013d
commit 851ed06769
4 changed files with 7 additions and 7 deletions
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2
nmigen/back/rtlil.py
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@ -445,7 +445,7 @@ def convert_fragment(builder, fragment, name, clock_domains):
cd = clock_domains[cd_name]
triggers.append(("posedge", xformer(cd.clk)))
if cd.async_reset:
triggers.append(("posedge", xformer(cd.rst)))
triggers.append(("posedge", xformer(cd.reset)))
for trigger in triggers:
with process.sync(*trigger) as sync: