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ClockDomain.{rst→reset}, for consistency with ResetInserter.

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nmigen.compat.ClockDomain would alias this, for Migen compatibility.
This commit is contained in:
whitequark 2018-12-12 09:49:02 +00:00
parent 4d3258013d
commit 851ed06769
4 changed files with 7 additions and 7 deletions
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6
nmigen/fhdl/cd.py
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@ -27,7 +27,7 @@ class ClockDomain:
clk : Signal, inout
The clock for this domain. Can be driven or used to drive other signals (preferably
in combinatorial context).
rst : Signal or None, inout
reset : Signal or None, inout
Reset signal for this domain. Can be driven or used to drive.
"""
def __init__(self, name=None, reset_less=False, async_reset=False):
@ -41,8 +41,8 @@ class ClockDomain:
self.clk = Signal(name=self.name + "_clk")
if reset_less:
self.rst = None
self.reset = None
else:
self.rst = Signal(name=self.name + "_rst")
self.reset = Signal(name=self.name + "_reset")
self.async_reset = async_reset

2
nmigen/fhdl/ir.py
View file

@ -53,7 +53,7 @@ class Fragment:
def prepare(self, ports, clock_domains):
from .xfrm import ResetInserter
resets = {cd.name: cd.rst for cd in clock_domains.values() if cd.rst is not None}
resets = {cd.name: cd.reset for cd in clock_domains.values() if cd.reset is not None}
frag = ResetInserter(resets)(self)
self_driven = union(s._lhs_signals() for s in self.statements)