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ClockDomain.{rst→reset}, for consistency with ResetInserter.

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nmigen.compat.ClockDomain would alias this, for Migen compatibility.
This commit is contained in:
whitequark 2018-12-12 09:49:02 +00:00
parent 4d3258013d
commit 851ed06769
4 changed files with 7 additions and 7 deletions
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4
examples/arst.py
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@ -17,5 +17,5 @@ class ClockDivisor:
sys = ClockDomain(async_reset=True) sys = ClockDomain(async_reset=True)
ctr = ClockDivisor(factor=16) ctr = ClockDivisor(factor=16)
frag = ctr.get_fragment(platform=None) frag = ctr.get_fragment(platform=None)
# print(rtlil.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys})) # print(rtlil.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))
print(verilog.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys})) print(verilog.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys}))

2
nmigen/back/rtlil.py
View file

@ -445,7 +445,7 @@ def convert_fragment(builder, fragment, name, clock_domains):
cd = clock_domains[cd_name] cd = clock_domains[cd_name]
triggers.append(("posedge", xformer(cd.clk))) triggers.append(("posedge", xformer(cd.clk)))
if cd.async_reset: if cd.async_reset:
triggers.append(("posedge", xformer(cd.rst))) triggers.append(("posedge", xformer(cd.reset)))
for trigger in triggers: for trigger in triggers:
with process.sync(*trigger) as sync: with process.sync(*trigger) as sync:

6
nmigen/fhdl/cd.py
View file

@ -27,7 +27,7 @@ class ClockDomain:
clk : Signal, inout clk : Signal, inout
The clock for this domain. Can be driven or used to drive other signals (preferably The clock for this domain. Can be driven or used to drive other signals (preferably
in combinatorial context). in combinatorial context).
rst : Signal or None, inout reset : Signal or None, inout
Reset signal for this domain. Can be driven or used to drive. Reset signal for this domain. Can be driven or used to drive.
""" """
def __init__(self, name=None, reset_less=False, async_reset=False): def __init__(self, name=None, reset_less=False, async_reset=False):
@ -41,8 +41,8 @@ class ClockDomain:
self.clk = Signal(name=self.name + "_clk") self.clk = Signal(name=self.name + "_clk")
if reset_less: if reset_less:
self.rst = None self.reset = None
else: else:
self.rst = Signal(name=self.name + "_rst") self.reset = Signal(name=self.name + "_reset")
self.async_reset = async_reset self.async_reset = async_reset

2
nmigen/fhdl/ir.py
View file

@ -53,7 +53,7 @@ class Fragment:
def prepare(self, ports, clock_domains): def prepare(self, ports, clock_domains):
from .xfrm import ResetInserter from .xfrm import ResetInserter
resets = {cd.name: cd.rst for cd in clock_domains.values() if cd.rst is not None} resets = {cd.name: cd.reset for cd in clock_domains.values() if cd.reset is not None}
frag = ResetInserter(resets)(self) frag = ResetInserter(resets)(self)
self_driven = union(s._lhs_signals() for s in self.statements) self_driven = union(s._lhs_signals() for s in self.statements)