back.verilog: refactor Yosys script generation. NFCI.

In commit 5f30bcbb, back.cxxsim gained a nicer way to generate
a script; this commit brings it to back.verilog too.

nmigen/back/verilog.py

@@ -10,39 +10,36 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog
     yosys = find_yosys(lambda ver: ver >= (0, 9))
     yosys_version = yosys.version()
 
-    attr_map = []
+    script = []
+    script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
+
+    if yosys_version >= (0, 9, 231):
+        # Yosys 0.9 release has buggy proc_prune.
+        script.append("delete w:$verilog_initial_trigger")
+        script.append("proc_prune")
+    script.append("proc_init")
+    script.append("proc_arst")
+    script.append("proc_dff")
+    script.append("proc_clean")
+    script.append("memory_collect")
+
     if strip_internal_attrs:
+        attr_map = []
         attr_map.append("-remove generator")
         attr_map.append("-remove top")
         attr_map.append("-remove src")
         attr_map.append("-remove nmigen.hierarchy")
         attr_map.append("-remove nmigen.decoding")
+        script.append("attrmap {}".format(" ".join(attr_map)))
+        script.append("attrmap -modattr {}".format(" ".join(attr_map)))
 
-    return yosys.run(["-q", "-"], """
+    script.append("write_verilog -norename {}".format(" ".join(write_verilog_opts)))
-# Convert nMigen's RTLIL to readable Verilog.
+
-read_ilang <<rtlil
+    return yosys.run(["-q", "-"], "\n".join(script),
-{}
+        # At the moment, Yosys always shows a warning indicating that not all processes can be
-rtlil
+        # translated to Verilog. We carefully emit only the processes that *can* be translated, and
-{prune}delete w:$verilog_initial_trigger
+        # squash this warning. Once Yosys' write_verilog pass is fixed, we should remove this.
-{prune}proc_prune
+        ignore_warnings=True)
-proc_init
-proc_arst
-proc_dff
-proc_clean
-memory_collect
-attrmap {attr_map}
-attrmap -modattr {attr_map}
-write_verilog -norename {write_verilog_opts}
-""".format(rtlil_text,
-        # Yosys 0.9 release has buggy proc_prune.
-        prune="# " if yosys_version < (0, 9, 231) else "",
-        attr_map=" ".join(attr_map),
-        write_verilog_opts=" ".join(write_verilog_opts),
-    ),
-    # At the moment, Yosys always shows a warning indicating that not all processes can be
-    # translated to Verilog. We carefully emit only the processes that *can* be translated, and
-    # squash this warning. Once Yosys' write_verilog pass is fixed, we should remove this.
-    ignore_warnings=True)
 
 
 def convert_fragment(*args, strip_internal_attrs=False, **kwargs):