hdl.dsl: type check when adding to m.domains.
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2 changed files with 16 additions and 0 deletions
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@ -9,6 +9,7 @@ from .._utils import flatten, bits_for, deprecated
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from .. import tracer
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from .ast import *
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from .ir import *
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from .cd import *
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from .xfrm import *
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@ -107,10 +108,16 @@ class _ModuleBuilderDomainSet:
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def __iadd__(self, domains):
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for domain in flatten([domains]):
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if not isinstance(domain, ClockDomain):
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raise TypeError("Only clock domains may be added to `m.domains`, not {!r}"
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.format(domain))
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self._builder._add_domain(domain)
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return self
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def __setattr__(self, name, domain):
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if not isinstance(domain, ClockDomain):
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raise TypeError("Only clock domains may be added to `m.domains`, not {!r}"
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.format(domain))
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self._builder._add_domain(domain)
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