hdl.dsl: type check when adding to m.domains.

nmigen/test/test_hdl_dsl.py

@@ -707,6 +707,15 @@ class DSLTestCase(FHDLTestCase):
         self.assertEqual(len(m._domains), 1)
         self.assertEqual(m._domains[0].name, "foo")
 
+    def test_domain_add_wrong(self):
+        m = Module()
+        with self.assertRaises(TypeError,
+                msg="Only clock domains may be added to `m.domains`, not 1"):
+            m.domains.foo = 1
+        with self.assertRaises(TypeError,
+                msg="Only clock domains may be added to `m.domains`, not 1"):
+            m.domains += 1
+
     def test_lower(self):
         m1 = Module()
         m1.d.comb += self.c1.eq(self.s1)