back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.

To track upstream changes.

nmigen/back/rtlil.py

@@ -955,9 +955,8 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                     # simulators to work properly, and is universally ignored by synthesizers,
                     # Verilator rejects it.
                     #
-                    # Running the Yosys proc_prune pass converts such pathological `always @*`
-                    # blocks to `assign` statements, so this workaround can be removed completely
-                    # once support for Yosys 0.9 is dropped.
+                    # Yosys >=0.9+3468 emits a better workaround on its own, so this code can be
+                    # removed completely once support for Yosys 0.9 is dropped.
                     if not stmt_compiler._has_rhs:
                         if verilog_trigger is None:
                             verilog_trigger = \

nmigen/back/verilog.py

@@ -13,11 +13,15 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog
     script = []
     script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
 
+    if yosys_version >= (0, 9, 3468):
+        # Yosys >=0.9+3468 (since commit 128522f1) emits the workaround for the `always @*`
+        # initial scheduling issue on its own.
+        script.append("delete w:$verilog_initial_trigger")
+
     if yosys_version >= (0, 9, 3527):
         # Yosys >=0.9+3527 (since commit 656ee70f) supports the `-nomux` option for the `proc`
         # script pass. Because the individual `proc_*` passes are not a stable interface,
         # `proc -nomux` is used instead, if available.
-        script.append("delete w:$verilog_initial_trigger")
         script.append("proc -nomux")
     else:
         # On earlier versions, use individual `proc_*` passes; this is a known range of Yosys