build.plat,vendor: automatically create sync domain from default_clk.
But only if it is not defined by the programmer. Closes #57.
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5 changed files with 87 additions and 19 deletions
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@ -7,6 +7,7 @@ import jinja2
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from .. import __version__
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from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.dsl import *
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from ..hdl.ir import *
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from ..back import rtlil, verilog
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@ -71,11 +72,27 @@ class Platform(ResourceManager, metaclass=ABCMeta):
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self.toolchain_program(products, name, **(program_opts or {}))
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@abstractmethod
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def create_missing_domain(self, name):
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if name == "sync" and self.default_clk is not None:
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clk_i = self.request(self.default_clk).i
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if self.default_rst is not None:
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rst_i = self.request(self.default_rst).i
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m = Module()
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m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
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m.d.comb += ClockSignal("sync").eq(clk_i)
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if self.default_rst is not None:
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m.d.comb += ResetSignal("sync").eq(rst_i)
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return m
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def prepare(self, fragment, name="top", **kwargs):
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assert not self._prepared
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self._prepared = True
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fragment = Fragment.get(fragment, self)
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fragment = fragment.prepare(ports=list(self.iter_ports()),
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missing_domain=self.create_missing_domain)
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def add_pin_fragment(pin, pin_fragment):
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pin_fragment = Fragment.get(pin_fragment, self)
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@ -226,9 +243,8 @@ class TemplatedPlatform(Platform):
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autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__)
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def emit_design(backend):
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return {"rtlil": rtlil, "verilog": verilog}[backend].convert(
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fragment, name=name, platform=self, ports=list(self.iter_ports()),
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missing_domain=lambda name: None)
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return {"rtlil": rtlil, "verilog": verilog}[backend].convert(fragment, name=name,
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ports=list(self.iter_ports()), missing_domain=lambda name: None)
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def emit_commands(format):
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commands = []
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