build.plat,vendor: automatically create sync domain from default_clk.

But only if it is not defined by the programmer.

Closes #57.
This commit is contained in:
whitequark 2019-08-03 18:36:58 +00:00
parent e0b54b417e
commit 8854ca03ae
5 changed files with 87 additions and 19 deletions

View file

@ -7,6 +7,7 @@ import jinja2
from .. import __version__
from ..hdl.ast import *
from ..hdl.cd import *
from ..hdl.dsl import *
from ..hdl.ir import *
from ..back import rtlil, verilog
@ -71,11 +72,27 @@ class Platform(ResourceManager, metaclass=ABCMeta):
self.toolchain_program(products, name, **(program_opts or {}))
@abstractmethod
def create_missing_domain(self, name):
if name == "sync" and self.default_clk is not None:
clk_i = self.request(self.default_clk).i
if self.default_rst is not None:
rst_i = self.request(self.default_rst).i
m = Module()
m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
m.d.comb += ClockSignal("sync").eq(clk_i)
if self.default_rst is not None:
m.d.comb += ResetSignal("sync").eq(rst_i)
return m
def prepare(self, fragment, name="top", **kwargs):
assert not self._prepared
self._prepared = True
fragment = Fragment.get(fragment, self)
fragment = fragment.prepare(ports=list(self.iter_ports()),
missing_domain=self.create_missing_domain)
def add_pin_fragment(pin, pin_fragment):
pin_fragment = Fragment.get(pin_fragment, self)
@ -226,9 +243,8 @@ class TemplatedPlatform(Platform):
autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__)
def emit_design(backend):
return {"rtlil": rtlil, "verilog": verilog}[backend].convert(
fragment, name=name, platform=self, ports=list(self.iter_ports()),
missing_domain=lambda name: None)
return {"rtlil": rtlil, "verilog": verilog}[backend].convert(fragment, name=name,
ports=list(self.iter_ports()), missing_domain=lambda name: None)
def emit_commands(format):
commands = []