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build.plat,vendor: allow clock constraints on arbitrary signals.

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Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.
This commit is contained in:
whitequark 2019-09-11 23:35:43 +00:00
parent d1779bdb59
commit 8c30147e39
4 changed files with 8 additions and 4 deletions
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4
nmigen/build/plat.py
View file

@ -296,6 +296,9 @@ class TemplatedPlatform(Platform):
else: else:
return " ".join(opts) return " ".join(opts)
def hierarchy(signal, separator):
return separator.join(name_map[signal][1:])
def verbose(arg): def verbose(arg):
if "NMIGEN_verbose" in os.environ: if "NMIGEN_verbose" in os.environ:
return arg return arg
@ -313,6 +316,7 @@ class TemplatedPlatform(Platform):
source = textwrap.dedent(source).strip() source = textwrap.dedent(source).strip()
compiled = jinja2.Template(source, trim_blocks=True, lstrip_blocks=True) compiled = jinja2.Template(source, trim_blocks=True, lstrip_blocks=True)
compiled.environment.filters["options"] = options compiled.environment.filters["options"] = options
compiled.environment.filters["hierarchy"] = hierarchy
except jinja2.TemplateSyntaxError as e: except jinja2.TemplateSyntaxError as e:
e.args = ("{} (at {}:{})".format(e.message, origin, e.lineno),) e.args = ("{} (at {}:{})".format(e.message, origin, e.lineno),)
raise raise

2
nmigen/vendor/lattice_ecp5.py vendored
View file

@ -209,7 +209,7 @@ class LatticeECP5Platform(TemplatedPlatform):
""", """,
"{{name}}.sdc": r""" "{{name}}.sdc": r"""
{% for signal, frequency in platform.iter_clock_constraints() -%} {% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -period {{1000000000/frequency}} [get_ports {{signal.name}}] create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
{% endfor %} {% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}} {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""", """,

2
nmigen/vendor/xilinx_7series.py vendored
View file

@ -106,7 +106,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
{% endfor %} {% endfor %}
{% endfor %} {% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%} {% for signal, frequency in platform.iter_clock_constraints() -%}
create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_ports {{signal.name}}] create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
{% endfor %} {% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}} {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""" """

4
nmigen/vendor/xilinx_spartan_3_6.py vendored
View file

@ -127,8 +127,8 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
{% endfor %} {% endfor %}
{% endfor %} {% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%} {% for signal, frequency in platform.iter_clock_constraints() -%}
NET "{{signal.name}}" TNM_NET="PRD{{signal.name}}"; NET "{{signal|hierarchy("/")}}" TNM_NET="PRD{{signal|hierarchy("/")}}";
TIMESPEC "TS{{signal.name}}"=PERIOD "PRD{{signal.name}}" {{1000000000/frequency}} ns HIGH 50%; TIMESPEC "TS{{signal|hierarchy("/")}}"=PERIOD "PRD{{signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
{% endfor %} {% endfor %}
{{get_override("add_constraints")|default("# (add_constraints placeholder)")}} {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
""" """