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hdl.mem: lower Memory directly to $mem_v2 RTLIL cell.

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The design decision of using split memory ports in the internal
representation (copied from Yosys) was misguided and caused no end
of misery. Remove any uses of `$memrd`/`$memwr` and lower memories
directly to a combined memory cell, currently the RTLIL one.
This commit is contained in:
Marcelina Kościelnicka 2023-09-01 05:22:46 +00:00 • committed by Catherine
parent fc85feb30d
commit 8c4a15ab92
10 changed files with 183 additions and 193 deletions
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38
amaranth/back/rtlil.py
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@ -863,49 +863,21 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
if sub_name is None:
sub_name = module.anonymous()
sub_params = OrderedDict()
if hasattr(subfragment, "parameters"):
for param_name, param_value in subfragment.parameters.items():
if isinstance(param_value, mem.Memory):
memory = param_value
if memory not in memories:
memories[memory] = module.memory(width=memory.width, size=memory.depth,
name=memory.name, attrs=memory.attrs)
addr_bits = bits_for(memory.depth)
data_parts = []
data_mask = (1 << memory.width) - 1
for addr in range(memory.depth):
if addr < len(memory.init):
data = memory.init[addr] & data_mask
else:
data = 0
data_parts.append("{:0{}b}".format(data, memory.width))
module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
"\\DATA": "{}'".format(memory.width * memory.depth) +
"".join(reversed(data_parts)),
}, params={
"MEMID": memories[memory],
"ABITS": addr_bits,
"WIDTH": memory.width,
"WORDS": memory.depth,
"PRIORITY": 0,
})
param_value = memories[memory]
sub_params[param_name] = param_value
sub_params = OrderedDict(getattr(subfragment, "parameters", {}))
sub_type, sub_port_map = \
_convert_fragment(builder, subfragment, name_map,
hierarchy=hierarchy + (sub_name,))
if sub_type == "$mem_v2" and "MEMID" not in sub_params:
sub_params["MEMID"] = "$" + sub_name
sub_ports = OrderedDict()
for port, value in sub_port_map.items():
if not isinstance(subfragment, ir.Instance):
for signal in value._rhs_signals():
compiler_state.resolve_curr(signal, prefix=sub_name)
if len(value) > 0:
if len(value) > 0 or sub_type == "$mem_v2":
sub_ports[port] = rhs_compiler(value)
module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params,