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hdl.mem: lower Memory directly to $mem_v2 RTLIL cell.

Browse source 
The design decision of using split memory ports in the internal
representation (copied from Yosys) was misguided and caused no end
of misery. Remove any uses of `$memrd`/`$memwr` and lower memories
directly to a combined memory cell, currently the RTLIL one.
This commit is contained in:
Marcelina Kościelnicka 2023-09-01 05:22:46 +00:00 • committed by Catherine
parent fc85feb30d
commit 8c4a15ab92
10 changed files with 183 additions and 193 deletions
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37
tests/test_hdl_ir.py
View file

@ -678,43 +678,6 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
)
""")
def setUp_memory(self):
self.m = Memory(width=8, depth=4)
self.fr = self.m.read_port().elaborate(platform=None)
self.fw = self.m.write_port().elaborate(platform=None)
self.f1 = Fragment()
self.f2 = Fragment()
self.f2.add_subfragment(self.fr)
self.f1.add_subfragment(self.f2)
self.f3 = Fragment()
self.f3.add_subfragment(self.fw)
self.f1.add_subfragment(self.f3)
def test_conflict_memory(self):
self.setUp_memory()
self.f1._resolve_hierarchy_conflicts(mode="silent")
self.assertEqual(self.f1.subfragments, [
(self.fr, None),
(self.fw, None),
])
def test_conflict_memory_error(self):
self.setUp_memory()
with self.assertRaisesRegex(DriverConflict,
r"^Memory 'm' is accessed from multiple fragments: top\.<unnamed #0>, "
r"top\.<unnamed #1>$"):
self.f1._resolve_hierarchy_conflicts(mode="error")
def test_conflict_memory_warning(self):
self.setUp_memory()
with self.assertWarnsRegex(DriverConflict,
(r"^Memory 'm' is accessed from multiple fragments: top.<unnamed #0>, "
r"top.<unnamed #1>; hierarchy will be flattened$")):
self.f1._resolve_hierarchy_conflicts(mode="warn")
def test_explicit_flatten(self):
self.f1 = Fragment()
self.f2 = Fragment()

4
tests/test_hdl_mem.py
View file

@ -58,8 +58,8 @@ class MemoryTestCase(FHDLTestCase):
self.assertEqual(len(rdport.addr), 2)
self.assertEqual(len(rdport.data), 8)
self.assertEqual(len(rdport.en), 1)
self.assertIsInstance(rdport.en, Const)
self.assertEqual(rdport.en.value, 1)
self.assertIsInstance(rdport.en, Signal)
self.assertEqual(rdport.en.reset, 1)
def test_read_port_non_transparent(self):
mem = Memory(width=8, depth=4)

16
tests/test_hdl_xfrm.py
View file

@ -547,16 +547,18 @@ class EnableInserterTestCase(FHDLTestCase):
def test_enable_read_port(self):
mem = Memory(width=8, depth=4)
f = EnableInserter(self.c1)(mem.read_port(transparent=False)).elaborate(platform=None)
self.assertRepr(f.named_ports["EN"][0], """
(m (sig c1) (sig mem_r_en) (const 1'd0))
mem.read_port(transparent=False)
f = EnableInserter(self.c1)(mem).elaborate(platform=None)
self.assertRepr(f.named_ports["RD_EN"][0], """
(cat (m (sig c1) (sig mem_r_en) (const 1'd0)))
""")
def test_enable_write_port(self):
mem = Memory(width=8, depth=4)
f = EnableInserter(self.c1)(mem.write_port()).elaborate(platform=None)
self.assertRepr(f.named_ports["EN"][0], """
(m
mem.write_port()
f = EnableInserter(self.c1)(mem).elaborate(platform=None)
self.assertRepr(f.named_ports["WR_EN"][0], """
(cat (m
(sig c1)
(cat
(cat
@ -571,7 +573,7 @@ class EnableInserterTestCase(FHDLTestCase):
)
)
(const 8'd0)
)
))
""")

47
tests/test_sim.py
View file

@ -697,7 +697,6 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
self.setUp_memory()
with self.assertSimulation(self.m) as sim:
def process():
self.assertEqual((yield self.rdport.data), 0xaa)
yield self.rdport.addr.eq(1)
yield
yield
@ -807,6 +806,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
self.m.submodules.rdport = self.rdport = self.memory.read_port()
with self.assertSimulation(self.m) as sim:
def process():
yield
self.assertEqual((yield self.rdport.data), 0xaa)
yield self.rdport.addr.eq(1)
yield
@ -815,6 +815,51 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
sim.add_clock(1e-6)
sim.add_sync_process(process)
def test_memory_transparency(self):
m = Module()
init = [0x11111111, 0x22222222, 0x33333333, 0x44444444]
m.submodules.memory = memory = Memory(width=32, depth=4, init=init)
rdport = memory.read_port()
wrport = memory.write_port(granularity=8)
with self.assertSimulation(m) as sim:
def process():
yield rdport.addr.eq(0)
yield
yield Settle()
self.assertEqual((yield rdport.data), 0x11111111)
yield rdport.addr.eq(1)
yield
yield Settle()
self.assertEqual((yield rdport.data), 0x22222222)
yield wrport.addr.eq(0)
yield wrport.data.eq(0x44444444)
yield wrport.en.eq(1)
yield
yield Settle()
self.assertEqual((yield rdport.data), 0x22222222)
yield wrport.addr.eq(1)
yield wrport.data.eq(0x55555555)
yield wrport.en.eq(1)
yield
yield Settle()
self.assertEqual((yield rdport.data), 0x22222255)
yield wrport.addr.eq(1)
yield wrport.data.eq(0x66666666)
yield wrport.en.eq(2)
yield rdport.en.eq(0)
yield
yield Settle()
self.assertEqual((yield rdport.data), 0x22222255)
yield wrport.addr.eq(1)
yield wrport.data.eq(0x77777777)
yield wrport.en.eq(4)
yield rdport.en.eq(1)
yield
yield Settle()
self.assertEqual((yield rdport.data), 0x22776655)
sim.add_clock(1e-6)
sim.add_sync_process(process)
@_ignore_deprecated
def test_sample_helpers(self):
m = Module()