lib.memory: improve and finish documentation.
This commit is contained in:
Catherine
parent
8faa6facfb
commit
8d44ec513d
6 changed files with 416 additions and 150 deletions
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@ -5,76 +5,100 @@ from collections.abc import MutableSequence
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from ..hdl import MemoryIdentity, MemoryInstance, Shape, ShapeCastable, Const
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from ..hdl._mem import MemorySimRead
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from ..utils import ceil_log2
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from .data import ArrayLayout
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from . import wiring
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from .. import tracer
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from . import wiring, data
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__all__ = ["Memory", "ReadPort", "WritePort"]
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class Memory(wiring.Component):
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"""A word addressable storage.
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"""Addressable array of rows.
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This :ref:`component <wiring>` is used to construct a memory array by first specifying its
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dimensions and initial contents using the :py:`shape`, :py:`depth`, and :py:`init` parameters,
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and then adding memory ports using the :meth:`read_port` and :meth:`write_port` methods.
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Because it is mutable, it should be created and used locally within
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the :ref:`elaborate <lang-elaboration>` method.
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The :py:`init` parameter and assignment to the :py:`init` attribute have the same effect, with
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:class:`Memory.Init` converting elements of the iterable to match :py:`shape` and using
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a default value for rows that are not explicitly initialized.
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.. warning::
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Uninitialized memories (including ASIC memories and some FPGA memories) are
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`not yet supported <https://github.com/amaranth-lang/amaranth/issues/270>`_, and
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the :py:`init` parameter must be always provided, if only as :py:`init=[]`.
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Parameters
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----------
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shape : :ref:`shape-like <lang-shapelike>` object
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The shape of a single element of the storage.
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depth : int
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Word count. This memory contains ``depth`` storage elements.
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init : iterable of int or of any objects accepted by ``shape.const()``
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Initial values. At power on, each storage element in this memory is initialized to
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the corresponding element of ``init``, if any, or to the default value of ``shape`` otherwise.
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Uninitialized memories are not currently supported.
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attrs : dict
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Dictionary of synthesis attributes.
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Shape of each memory row.
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depth : :class:`int`
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Number of memory rows.
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init : iterable of initial values
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Initial values for memory rows.
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Attributes
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----------
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shape : :ref:`shape-like <lang-shapelike>`
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depth : int
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init : :class:`Memory.Init`
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attrs : dict
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r_ports : tuple of :class:`ReadPort`
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w_ports : tuple of :class:`WritePort`
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Platform overrides
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------------------
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Define the :py:`get_memory()` platform method to override the implementation of
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:class:`Memory`, e.g. to instantiate library cells directly.
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"""
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class Init(MutableSequence):
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"""Initial data of a :class:`Memory`.
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"""Memory initialization data.
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This is a container implementing the ``MutableSequence`` protocol, enforcing two constraints:
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This is a special container used only for the :attr:`Memory.init` attribute. It is similar
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to :class:`list`, but does not support inserting or deleting elements; its length is always
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the same as the depth of the memory it belongs to.
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- the length is immutable and must equal ``depth``
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- if ``shape`` is a :class:`ShapeCastable`, each element can be cast to ``shape`` via :py:`shape.const()`
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- otherwise, each element is an :py:`int`
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If :py:`shape` is a :ref:`custom shape-castable object <lang-shapecustom>`, then:
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* Each element must be convertible to :py:`shape` via :meth:`.ShapeCastable.const`, and
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* Elements that are not explicitly initialized default to :py:`shape.const(None)`.
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Otherwise (when :py:`shape` is a :class:`.Shape`):
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* Each element must be an :class:`int`, and
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* Elements that are not explicitly initialized default to :py:`0`.
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"""
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def __init__(self, items, *, shape, depth):
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def __init__(self, elems, *, shape, depth):
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Shape.cast(shape)
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if not isinstance(depth, int) or depth < 0:
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raise TypeError("Memory depth must be a non-negative integer, not {!r}"
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.format(depth))
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self._shape = shape
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self._depth = depth
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if isinstance(shape, ShapeCastable):
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self._items = [None] * depth
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default = Const.cast(shape.const(None)).value
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self._raw = [default] * depth
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self._elems = [None] * depth
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self._raw = [Const.cast(shape.const(None)).value] * depth
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else:
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self._raw = self._items = [0] * depth
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self._elems = [0] * depth
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self._raw = self._elems # intentionally mutably aliased
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try:
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for idx, item in enumerate(items):
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self[idx] = item
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for index, item in enumerate(elems):
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self[index] = item
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except (TypeError, ValueError) as e:
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raise type(e)("Memory initialization value at address {:x}: {}"
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.format(idx, e)) from None
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.format(index, e)) from None
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@property
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def shape(self):
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return self._shape
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# TODO: redundant with __len__
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@property
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def depth(self):
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return self._depth
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def __getitem__(self, index):
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return self._items[index]
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return self._elems[index]
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def __setitem__(self, index, value):
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if isinstance(index, slice):
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start, stop, step = index.indices(len(self._items))
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indices = range(start, stop, step)
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indices = range(*index.indices(len(self._elems)))
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if len(value) != len(indices):
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raise ValueError("Changing length of Memory.init is not allowed")
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for actual_index, actual_value in zip(indices, value):
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@ -84,48 +108,45 @@ class Memory(wiring.Component):
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self._raw[index] = Const.cast(self._shape.const(value)).value
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else:
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value = operator.index(value)
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self._items[index] = value
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# self._raw[index] assigned by the following line
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self._elems[index] = value
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def __delitem__(self, index):
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raise TypeError("Deleting items from Memory.init is not allowed")
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raise TypeError("Deleting elements from Memory.init is not allowed")
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def insert(self, index, value):
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raise TypeError("Inserting items into Memory.init is not allowed")
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""":meta private:"""
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raise TypeError("Inserting elements into Memory.init is not allowed")
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def __len__(self):
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return self._depth
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@property
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def depth(self):
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return self._depth
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@property
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def shape(self):
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return self._shape
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def __repr__(self):
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return f"Memory.Init({self._items!r})"
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return f"Memory.Init({self._elems!r})"
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def __init__(self, *, depth, shape, init, attrs=None, src_loc_at=0, src_loc=None):
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# shape and depth validation performed in Memory.Init constructor.
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self._depth = depth
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def __init__(self, *, shape, depth, init, attrs=None, src_loc_at=0):
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# shape and depth validation is performed in Memory.Init()
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self._shape = shape
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self._depth = depth
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self._init = Memory.Init(init, shape=shape, depth=depth)
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self._attrs = {} if attrs is None else dict(attrs)
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self.src_loc = src_loc or tracer.get_src_loc(src_loc_at=src_loc_at)
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self._identity = MemoryIdentity()
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self._r_ports: "list[ReadPort]" = []
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self._w_ports: "list[WritePort]" = []
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super().__init__(wiring.Signature({}))
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self.src_loc = tracer.get_src_loc(src_loc_at=src_loc_at)
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@property
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def depth(self):
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return self._depth
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self._identity = MemoryIdentity()
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self._read_ports: "list[ReadPort]" = []
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self._write_ports: "list[WritePort]" = []
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super().__init__(wiring.Signature({}))
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@property
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def shape(self):
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return self._shape
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@property
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def depth(self):
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return self._depth
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@property
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def init(self):
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return self._init
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@ -139,43 +160,90 @@ class Memory(wiring.Component):
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return self._attrs
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def read_port(self, *, domain="sync", transparent_for=()):
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"""Adds a new read port and returns it.
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"""Request a read port.
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Equivalent to creating a :class:`ReadPort` with a signature of :py:`ReadPort.Signature(addr_width=ceil_log2(self.depth), shape=self.shape)`
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If :py:`domain` is :py:`"comb"`, the created read port is asynchronous and always enabled
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(with its enable input is tied to :py:`Const(1)`), and its data output always reflects
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the contents of the selected row. Otherwise, the created read port is synchronous,
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and its data output is updated with the contents of the selected row at each
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:ref:`active edge <lang-sync>` of :py:`domain` where the enable input is asserted.
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The :py:`transparent_for` parameter specifies the *transparency set* of this port: zero or
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more :class:`WritePort`\\ s, all of which must belong to the same memory and clock domain.
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If another port writes to a memory row at the same time as this port reads from the same
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memory row, and that write port is a part of the transparency set, then this port retrieves
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the new contents of the row; otherwise, this port retrieves the old contents of the row.
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If another write port belonging to a different clock domain updates a memory row that this
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port is reading at the same time, the behavior is undefined.
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The signature of the returned port is
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:py:`ReadPort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth))`.
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Returns
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-------
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:class:`ReadPort`
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"""
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signature = ReadPort.Signature(addr_width=ceil_log2(self.depth), shape=self.shape)
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signature = ReadPort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth))
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return ReadPort(signature, memory=self, domain=domain, transparent_for=transparent_for)
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@property
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def r_ports(self):
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"""Returns a tuple of all read ports defined so far."""
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return tuple(self._r_ports)
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def write_port(self, *, domain="sync", granularity=None):
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"""Adds a new write port and returns it.
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"""Request a write port.
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Equivalent to creating a :class:`WritePort` with a signature of :py:`WritePort.Signature(addr_width=ceil_log2(self.depth), shape=self.shape, granularity=granularity)`
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The created write port is synchronous, updating the contents of the selected row at each
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:ref:`active edge <lang-sync>` of :py:`domain` where the enable input is asserted.
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Specifying a *granularity* when :py:`shape` is :func:`unsigned(width) <.unsigned>` or
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:class:`data.ArrayLayout(_, width) <.data.ArrayLayout>` makes it possible to partially
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update a memory row. In this case, :py:`granularity` must be an integer that evenly divides
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:py:`width`, and the memory row is split into :py:`width // granularity` equally sized
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parts, each of which is updated if the corresponding bit of the enable input is asserted.
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The signature of the new port is
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:py:`WritePort.Signature(shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity)`.
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Returns
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-------
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:class:`WritePort`
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"""
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signature = WritePort.Signature(addr_width=ceil_log2(self.depth), shape=self.shape, granularity=granularity)
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signature = WritePort.Signature(
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shape=self.shape, addr_width=ceil_log2(self.depth), granularity=granularity)
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return WritePort(signature, memory=self, domain=domain)
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# TODO: rename to read_ports
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@property
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def r_ports(self):
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"""All read ports defined so far.
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This property is provided for the :py:`platform.get_memory()` override.
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"""
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return tuple(self._read_ports)
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# TODO: rename to write_ports
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@property
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def w_ports(self):
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"""Returns a tuple of all write ports defined so far."""
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return tuple(self._w_ports)
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"""All write ports defined so far.
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This property is provided for the :py:`platform.get_memory()` override.
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"""
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return tuple(self._write_ports)
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def elaborate(self, platform):
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if hasattr(platform, "get_memory"):
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return platform.get_memory(self)
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shape = Shape.cast(self.shape)
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instance = MemoryInstance(identity=self._identity, width=shape.width, depth=self.depth, init=self.init._raw, attrs=self.attrs, src_loc=self.src_loc)
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w_ports = {}
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for port in self._w_ports:
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idx = instance.write_port(domain=port.domain, addr=port.addr, data=port.data, en=port.en)
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w_ports[port] = idx
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for port in self._r_ports:
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transparent_for = [w_ports[write_port] for write_port in port.transparent_for]
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instance.read_port(domain=port.domain, data=port.data, addr=port.addr, en=port.en, transparent_for=transparent_for)
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instance = MemoryInstance(identity=self._identity, width=shape.width, depth=self.depth,
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init=self.init._raw, attrs=self.attrs, src_loc=self.src_loc)
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write_ports = {}
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for port in self._write_ports:
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write_ports[port] = instance.write_port(
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domain=port.domain, addr=port.addr, data=port.data, en=port.en)
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for port in self._read_ports:
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transparent_for = tuple(write_ports[write_port] for write_port in port.transparent_for)
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instance.read_port(
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domain=port.domain, data=port.data, addr=port.addr, en=port.en,
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transparent_for=transparent_for)
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return instance
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def __getitem__(self, index):
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@ -184,48 +252,44 @@ class Memory(wiring.Component):
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class ReadPort:
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"""A memory read port.
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"""A read memory port.
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Parameters
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----------
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signature : :class:`ReadPort.Signature`
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The signature of the port.
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memory : :class:`Memory`
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Memory associated with the port.
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domain : str
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Clock domain. Defaults to ``"sync"``. If set to ``"comb"``, the port is asynchronous.
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Otherwise, the read data becomes available on the next clock cycle.
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transparent_for : iterable of :class:`WritePort`
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The set of write ports that this read port should be transparent with. All ports
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must belong to the same memory and the same clock domain.
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Memory read ports, which are :ref:`interface objects <wiring>`, can be constructed by calling
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:meth:`Memory.read_port` or via :meth:`ReadPort.Signature.create() <.Signature.create>`.
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An asynchronous (:py:`"comb"` domain) memory read port is always enabled. The :py:`en` input of
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such a port is tied to :py:`Const(1)`.
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Attributes
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----------
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signature : :class:`ReadPort.Signature`
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memory : :class:`Memory`
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domain : str
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transparent_for : tuple of :class:`WritePort`
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Signature of this memory port.
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memory : :class:`Memory` or :py:`None`
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Memory associated with this memory port.
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domain : :class:`str`
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Name of this memory port's clock domain. For asynchronous ports, :py:`"comb"`.
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transparent_for : :class:`tuple` of :class:`WritePort`
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Transparency set of this memory port.
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"""
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class Signature(wiring.Signature):
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"""A signature of a read port.
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"""Signature of a memory read port.
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Parameters
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----------
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addr_width : int
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Address width in bits. If the port is associated with a :class:`Memory`,
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it must be equal to :py:`ceil_log2(memory.depth)`.
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addr_width : :class:`int`
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Width of the address port.
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shape : :ref:`shape-like <lang-shapelike>` object
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The shape of the port data. If the port is associated with a :class:`Memory`,
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it must be equal to its element shape.
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Shape of the data port.
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Members
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-------
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addr: :py:`unsigned(data_width)`
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data: ``shape``
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en: :py:`unsigned(1)`
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The enable signal. If ``domain == "comb"``, this is tied to ``Const(1)``.
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Otherwise it is a signal with ``init=1``.
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en: :py:`In(1, init=1)`
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Enable input.
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addr: :py:`In(addr_width)`
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Address input.
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data: :py:`Out(shape)`
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Data output.
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"""
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def __init__(self, *, addr_width, shape):
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@ -234,12 +298,13 @@ class ReadPort:
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self._addr_width = addr_width
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self._shape = shape
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super().__init__({
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"en": wiring.In(1, init=1),
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"addr": wiring.In(addr_width),
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"data": wiring.Out(shape),
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"en": wiring.In(1, init=1),
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})
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def create(self, *, path=None, src_loc_at=0):
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""":meta private:""" # work around Sphinx bug
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return ReadPort(self, memory=None, domain="sync", path=path, src_loc_at=1 + src_loc_at)
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@property
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@ -262,7 +327,7 @@ class ReadPort:
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def __init__(self, signature, *, memory, domain, transparent_for=(), path=None, src_loc_at=0):
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if not isinstance(signature, ReadPort.Signature):
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raise TypeError(f"Expected `ReadPort.Signature`, not {signature!r}")
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if memory is not None:
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if memory is not None: # may be None if created via `Signature.create()`
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if not isinstance(memory, Memory):
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raise TypeError(f"Expected `Memory` or `None`, not {memory!r}")
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if signature.shape != memory.shape or Shape.cast(signature.shape) != Shape.cast(memory.shape):
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@ -275,7 +340,7 @@ class ReadPort:
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for port in transparent_for:
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if not isinstance(port, WritePort):
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raise TypeError("`transparent_for` must contain only `WritePort` instances")
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if memory is not None and port not in memory._w_ports:
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if memory is not None and port not in memory._write_ports:
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raise ValueError("Transparent write ports must belong to the same memory")
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if port.domain != domain:
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raise ValueError("Transparent write ports must belong to the same domain")
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@ -287,7 +352,7 @@ class ReadPort:
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if domain == "comb":
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self.en = Const(1)
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if memory is not None:
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memory._r_ports.append(self)
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memory._read_ports.append(self)
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@property
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def signature(self):
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@ -307,49 +372,50 @@ class ReadPort:
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class WritePort:
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||||
"""A memory write port.
|
||||
"""A write memory port.
|
||||
|
||||
Parameters
|
||||
----------
|
||||
signature : :class:`WritePort.Signature`
|
||||
The signature of the port.
|
||||
memory : :class:`Memory` or ``None``
|
||||
Memory associated with the port.
|
||||
domain : str
|
||||
Clock domain. Defaults to ``"sync"``. Writes have a latency of 1 clock cycle.
|
||||
Memory write ports, which are :ref:`interface objects <wiring>`, can be constructed by calling
|
||||
:meth:`Memory.write_port` or via :meth:`WritePort.Signature.create() <.Signature.create>`.
|
||||
|
||||
Attributes
|
||||
----------
|
||||
signature : :class:`WritePort.Signature`
|
||||
memory : :class:`Memory`
|
||||
domain : str
|
||||
Signature of this memory port.
|
||||
memory : :class:`Memory` or :py:`None`
|
||||
Memory associated with this memory port.
|
||||
domain : :class:`str`
|
||||
Name of this memory port's clock domain. Never :py:`"comb"`.
|
||||
"""
|
||||
|
||||
class Signature(wiring.Signature):
|
||||
"""A signature of a write port.
|
||||
"""Signature of a memory write port.
|
||||
|
||||
Width of the enable input is determined as follows:
|
||||
|
||||
* If :py:`granularity` is :py:`None`,
|
||||
then :py:`en_width == 1`.
|
||||
* If :py:`shape` is :func:`unsigned(data_width) <.unsigned>`,
|
||||
then :py:`en_width == data_width // granularity`.
|
||||
* If :py:`shape` is :class:`data.ArrayLayout(_, elem_count) <.data.ArrayLayout>`,
|
||||
then :py:`en_width == elem_count // granularity`.
|
||||
|
||||
Parameters
|
||||
----------
|
||||
addr_width : int
|
||||
Address width in bits. If the port is associated with a :class:`Memory`,
|
||||
it must be equal to :py:`ceil_log2(memory.depth)`.
|
||||
addr_width : :class:`int`
|
||||
Width of the address port.
|
||||
shape : :ref:`shape-like <lang-shapelike>` object
|
||||
The shape of the port data. If the port is associated with a :class:`Memory`,
|
||||
it must be equal to its element shape.
|
||||
granularity : int or ``None``
|
||||
Port granularity. If ``None``, the entire storage element is written at once.
|
||||
Otherwise, determines the size of access covered by a single bit of ``en``.
|
||||
One of the following must hold:
|
||||
|
||||
- ``granularity is None``, in which case ``en_width == 1``, or
|
||||
- ``shape == unsigned(data_width)`` and ``data_width == 0 or data_width % granularity == 0`` in which case ``en_width == data_width // granularity`` (or 0 if ``data_width == 0``)
|
||||
- ``shape == amaranth.lib.data.ArrayLayout(_, elem_count)`` and ``elem_count == 0 or elem_count % granularity == 0`` in which case ``en_width == elem_count // granularity`` (or 0 if ``elem_count == 0``)
|
||||
Shape of the data port.
|
||||
granularity : :class:`int` or :py:`None`
|
||||
Granularity of memory access.
|
||||
|
||||
Members
|
||||
-------
|
||||
addr: :py:`unsigned(data_width)`
|
||||
data: ``shape``
|
||||
en: :py:`unsigned(en_width)`
|
||||
en: :py:`In(en_width)`
|
||||
Enable input.
|
||||
addr: :py:`In(addr_width)`
|
||||
Address input.
|
||||
data: :py:`In(shape)`
|
||||
Data input.
|
||||
"""
|
||||
|
||||
def __init__(self, *, addr_width, shape, granularity=None):
|
||||
|
|
@ -374,7 +440,7 @@ class WritePort:
|
|||
raise ValueError("Granularity must divide data width")
|
||||
else:
|
||||
en_width = actual_shape.width // granularity
|
||||
elif isinstance(shape, ArrayLayout):
|
||||
elif isinstance(shape, data.ArrayLayout):
|
||||
if shape.length == 0:
|
||||
en_width = 0
|
||||
elif granularity == 0:
|
||||
|
|
@ -386,12 +452,13 @@ class WritePort:
|
|||
else:
|
||||
raise TypeError("Granularity can only be specified for plain unsigned `Shape` or `ArrayLayout`")
|
||||
super().__init__({
|
||||
"en": wiring.In(en_width),
|
||||
"addr": wiring.In(addr_width),
|
||||
"data": wiring.In(shape),
|
||||
"en": wiring.In(en_width),
|
||||
})
|
||||
|
||||
def create(self, *, path=None, src_loc_at=0):
|
||||
""":meta private:""" # work around Sphinx bug
|
||||
return WritePort(self, memory=None, domain="sync", path=path, src_loc_at=1 + src_loc_at)
|
||||
|
||||
@property
|
||||
|
|
@ -420,7 +487,7 @@ class WritePort:
|
|||
def __init__(self, signature, *, memory, domain, path=None, src_loc_at=0):
|
||||
if not isinstance(signature, WritePort.Signature):
|
||||
raise TypeError(f"Expected `WritePort.Signature`, not {signature!r}")
|
||||
if memory is not None:
|
||||
if memory is not None: # may be None if created via `Signature.create()`
|
||||
if not isinstance(memory, Memory):
|
||||
raise TypeError(f"Expected `Memory` or `None`, not {memory!r}")
|
||||
if signature.shape != memory.shape or Shape.cast(signature.shape) != Shape.cast(memory.shape):
|
||||
|
|
@ -436,7 +503,7 @@ class WritePort:
|
|||
self._domain = domain
|
||||
self.__dict__.update(signature.members.create(path=path, src_loc_at=1 + src_loc_at))
|
||||
if memory is not None:
|
||||
memory._w_ports.append(self)
|
||||
memory._write_ports.append(self)
|
||||
|
||||
@property
|
||||
def signature(self):
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue