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back.rtlil: more consistent prefixing for subfragment port wires.

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whitequark 2018-12-21 04:21:11 +00:00
parent b0bd7bfaca
commit 8d58cbf230
1 changed files with 3 additions and 5 deletions
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8
nmigen/back/rtlil.py
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@ -645,11 +645,9 @@ def convert_fragment(builder, fragment, name, top):
sub_ports = OrderedDict() sub_ports = OrderedDict()
for port, value in sub_port_map.items(): for port, value in sub_port_map.items():
if isinstance(value, ast.Signal): for signal in value._rhs_signals():
sigspec = compiler_state.resolve_curr(value, prefix=sub_name) compiler_state.resolve_curr(signal, prefix=sub_name)
else: sub_ports[port] = rhs_compiler(value)
sigspec = rhs_compiler(value)
sub_ports[port] = sigspec
module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params) module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params)