parent
b227352258
commit
8deb13cea3
7 changed files with 71 additions and 57 deletions
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@ -4,11 +4,11 @@ from ..back.pysim import *
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from ..lib.cdc import *
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class MultiRegTestCase(FHDLTestCase):
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class FFSynchronizerTestCase(FHDLTestCase):
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def test_basic(self):
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i = Signal()
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o = Signal()
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frag = MultiReg(i, o)
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frag = FFSynchronizer(i, o)
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with Simulator(frag) as sim:
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sim.add_clock(1e-6)
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def process():
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@ -26,7 +26,7 @@ class MultiRegTestCase(FHDLTestCase):
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def test_reset_value(self):
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i = Signal(reset=1)
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o = Signal()
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frag = MultiReg(i, o, reset=1)
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frag = FFSynchronizer(i, o, reset=1)
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with Simulator(frag) as sim:
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sim.add_clock(1e-6)
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def process():
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