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lib.cdc: MultiReg→FFSynchronizer.

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Fixes #229.
This commit is contained in:
whitequark 2019-09-23 14:17:44 +00:00
parent b227352258
commit 8deb13cea3
7 changed files with 71 additions and 57 deletions
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8
nmigen/vendor/xilinx_7series.py vendored
View file

@ -361,10 +361,10 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
)
return m
def get_multi_reg(self, multireg):
def get_ff_sync(self, ff_sync):
m = Module()
for i, o in zip((multireg.i, *multireg._regs), multireg._regs):
for i, o in zip((ff_sync.i, *ff_sync._stages), ff_sync._stages):
o.attrs["ASYNC_REG"] = "TRUE"
m.d[multireg._o_domain] += o.eq(i)
m.d.comb += multireg.o.eq(multireg._regs[-1])
m.d[ff_sync._o_domain] += o.eq(i)
m.d.comb += ff_sync.o.eq(ff_sync._stages[-1])
return m

8
nmigen/vendor/xilinx_spartan_3_6.py vendored
View file

@ -411,12 +411,12 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
)
return m
def get_multi_reg(self, multireg):
def get_ff_sync(self, ff_sync):
m = Module()
for i, o in zip((multireg.i, *multireg._regs), multireg._regs):
for i, o in zip((ff_sync.i, *ff_sync._stages), ff_sync._stages):
o.attrs["ASYNC_REG"] = "TRUE"
m.d[multireg._o_domain] += o.eq(i)
m.d.comb += multireg.o.eq(multireg._regs[-1])
m.d[ff_sync._o_domain] += o.eq(i)
m.d.comb += ff_sync.o.eq(multireg._stages[-1])
return m