build.dsl: add conn argument to Connector.
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@ -210,10 +210,10 @@ class Resource(Subsignal):
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class Connector:
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def __init__(self, name, number, io):
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def __init__(self, name, number, io, *, conn=None):
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self.name = name
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self.number = number
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self.mapping = OrderedDict()
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mapping = OrderedDict()
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if isinstance(io, dict):
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for conn_pin, plat_pin in io.items():
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@ -223,18 +223,29 @@ class Connector:
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if not isinstance(plat_pin, str):
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raise TypeError("Platform pin name must be a string, not {!r}"
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.format(plat_pin))
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self.mapping[conn_pin] = plat_pin
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mapping[conn_pin] = plat_pin
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elif isinstance(io, str):
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for conn_pin, plat_pin in enumerate(io.split(), start=1):
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if plat_pin == "-":
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continue
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self.mapping[str(conn_pin)] = plat_pin
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mapping[str(conn_pin)] = plat_pin
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else:
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raise TypeError("Connector I/Os must be a dictionary or a string, not {!r}"
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.format(io))
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if conn is not None:
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conn_name, conn_number = conn
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if not (isinstance(conn_name, str) and isinstance(conn_number, int)):
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raise TypeError("Connector must be None or a pair of string and integer, not {!r}"
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.format(conn))
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for conn_pin, plat_pin in mapping.items():
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mapping[conn_pin] = "{}_{}:{}".format(conn_name, conn_number, plat_pin)
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self.mapping = mapping
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def __repr__(self):
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return "(connector {} {} {})".format(self.name, self.number,
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" ".join("{}=>{}".format(conn, plat)
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@ -278,6 +278,19 @@ class ConnectorTestCase(FHDLTestCase):
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("DP1", "A1"),
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]))
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def test_conn(self):
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c = Connector("pmod", 0, "0 1 2 3 - - 4 5 6 7 - -", conn=("expansion", 0))
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self.assertEqual(c.mapping, OrderedDict([
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("1", "expansion_0:0"),
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("2", "expansion_0:1"),
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("3", "expansion_0:2"),
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("4", "expansion_0:3"),
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("7", "expansion_0:4"),
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("8", "expansion_0:5"),
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("9", "expansion_0:6"),
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("10", "expansion_0:7"),
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]))
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def test_wrong_io(self):
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with self.assertRaises(TypeError,
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msg="Connector I/Os must be a dictionary or a string, not []"):
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@ -168,6 +168,27 @@ class ResourceManagerTestCase(FHDLTestCase):
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("spi_0__mosi__io", ["B3"], {}),
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])
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def test_request_via_nested_connector(self):
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new_connectors = [
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Connector("pmod_extension", 0, "1 2 3 4 - -", conn=("pmod", 0)),
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]
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self.cm.add_connectors(new_connectors)
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self.cm.add_resources([
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Resource("spi", 0,
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Subsignal("ss", Pins("1", conn=("pmod_extension", 0))),
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Subsignal("clk", Pins("2", conn=("pmod_extension", 0))),
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Subsignal("miso", Pins("3", conn=("pmod_extension", 0))),
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Subsignal("mosi", Pins("4", conn=("pmod_extension", 0))),
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)
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])
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spi0 = self.cm.request("spi", 0)
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self.assertEqual(list(self.cm.iter_port_constraints()), [
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("spi_0__ss__io", ["B0"], {}),
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("spi_0__clk__io", ["B1"], {}),
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("spi_0__miso__io", ["B2"], {}),
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("spi_0__mosi__io", ["B3"], {}),
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])
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def test_request_clock(self):
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clk100 = self.cm.request("clk100", 0)
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clk50 = self.cm.request("clk50", 0, dir="i")
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